3,281 research outputs found
The Road to Quantum Computational Supremacy
We present an idiosyncratic view of the race for quantum computational
supremacy. Google's approach and IBM challenge are examined. An unexpected
side-effect of the race is the significant progress in designing fast classical
algorithms. Quantum supremacy, if achieved, won't make classical computing
obsolete.Comment: 15 pages, 1 figur
An FPGA-based system for generalised electron devices testing
Electronic systems are becoming more and more ubiquitous as our world digitises. Simultaneously, even basic components are experiencing a wave of improvements with new transistors, memristors, voltage/current references, data converters, etc, being designed every year by hundreds of R &D groups world-wide. To date, the workhorse for testing all these designs has been a suite of lab instruments including oscilloscopes and signal generators, to mention the most popular. However, as components become more complex and pin numbers soar, the need for more parallel and versatile testing tools also becomes more pressing. In this work, we describe and benchmark an FPGA system developed that addresses this need. This general purpose testing system features a 64-channel source-meter unit, and [Formula: see text] banks of 32 digital pins for digital I/O. We demonstrate that this bench-top system can obtain [Formula: see text] current noise floor, [Formula: see text] pulse delivery at [Formula: see text] and [Formula: see text] maximum current drive/channel. We then showcase the instrument's use in performing a selection of three characteristic measurement tasks: (a) current-voltage characterisation of a diode and a transistor, (b) fully parallel read-out of a memristor crossbar array and (c) an integral non-linearity test on a DAC. This work introduces a down-scaled electronics laboratory packaged in a single instrument which provides a shift towards more affordable, reliable, compact and multi-functional instrumentation for emerging electronic technologies
Accelerate & Actualize: Can 2D Materials Bridge the Gap Between Neuromorphic Hardware and the Human Brain?
Two-dimensional (2D) materials present an exciting opportunity for devices
and systems beyond the von Neumann computing architecture paradigm due to their
diversity of electronic structure, physical properties, and atomically-thin,
van der Waals structures that enable ease of integration with conventional
electronic materials and silicon-based hardware. All major classes of
non-volatile memory (NVM) devices have been demonstrated using 2D materials,
including their operation as synaptic devices for applications in neuromorphic
computing hardware. Their atomically-thin structure, superior physical
properties, i.e., mechanical strength, electrical and thermal conductivity, as
well as gate-tunable electronic properties provide performance advantages and
novel functionality in NVM devices and systems. However, device performance and
variability as compared to incumbent materials and technology remain major
concerns for real applications. Ultimately, the progress of 2D materials as a
novel class of electronic materials and specifically their application in the
area of neuromorphic electronics will depend on their scalable synthesis in
thin-film form with desired crystal quality, defect density, and phase purity.Comment: Neuromorphic Computing, 2D Materials, Heterostructures, Emerging
Memory Devices, Resistive, Phase-Change, Ferroelectric, Ferromagnetic,
Crossbar Array, Machine Learning, Deep Learning, Spiking Neural Network
Soft eSkin:distributed touch sensing with harmonized energy and computing
Inspired by biology, significant advances have been made in the field of electronic skin (eSkin) or tactile skin. Many of these advances have come through mimicking the morphology of human skin and by distributing few touch sensors in an area. However, the complexity of human skin goes beyond mimicking few morphological features or using few sensors. For example, embedded computing (e.g. processing of tactile data at the point of contact) is centric to the human skin as some neuroscience studies show. Likewise, distributed cell or molecular energy is a key feature of human skin. The eSkin with such features, along with distributed and embedded sensors/electronics on soft substrates, is an interesting topic to explore. These features also make eSkin significantly different from conventional computing. For example, unlike conventional centralized computing enabled by miniaturized chips, the eSkin could be seen as a flexible and wearable large area computer with distributed sensors and harmonized energy. This paper discusses these advanced features in eSkin, particularly the distributed sensing harmoniously integrated with energy harvesters, storage devices and distributed computing to read and locally process the tactile sensory data. Rapid advances in neuromorphic hardware, flexible energy generation, energy-conscious electronics, flexible and printed electronics are also discussed. This article is part of the theme issue ‘Harmonizing energy-autonomous computing and intelligence’
Pruning random resistive memory for optimizing analogue AI
The rapid advancement of artificial intelligence (AI) has been marked by the
large language models exhibiting human-like intelligence. However, these models
also present unprecedented challenges to energy consumption and environmental
sustainability. One promising solution is to revisit analogue computing, a
technique that predates digital computing and exploits emerging analogue
electronic devices, such as resistive memory, which features in-memory
computing, high scalability, and nonvolatility. However, analogue computing
still faces the same challenges as before: programming nonidealities and
expensive programming due to the underlying devices physics. Here, we report a
universal solution, software-hardware co-design using structural
plasticity-inspired edge pruning to optimize the topology of a randomly
weighted analogue resistive memory neural network. Software-wise, the topology
of a randomly weighted neural network is optimized by pruning connections
rather than precisely tuning resistive memory weights. Hardware-wise, we reveal
the physical origin of the programming stochasticity using transmission
electron microscopy, which is leveraged for large-scale and low-cost
implementation of an overparameterized random neural network containing
high-performance sub-networks. We implemented the co-design on a 40nm 256K
resistive memory macro, observing 17.3% and 19.9% accuracy improvements in
image and audio classification on FashionMNIST and Spoken digits datasets, as
well as 9.8% (2%) improvement in PR (ROC) in image segmentation on DRIVE
datasets, respectively. This is accompanied by 82.1%, 51.2%, and 99.8%
improvement in energy efficiency thanks to analogue in-memory computing. By
embracing the intrinsic stochasticity and in-memory computing, this work may
solve the biggest obstacle of analogue computing systems and thus unleash their
immense potential for next-generation AI hardware
2022 roadmap on neuromorphic computing and engineering
Modern computation based on von Neumann architecture is now a mature cutting-edge science. In the von Neumann architecture, processing and memory units are implemented as separate blocks interchanging data intensively and continuously. This data transfer is responsible for a large part of the power consumption. The next generation computer technology is expected to solve problems at the exascale with 10 calculations each second. Even though these future computers will be incredibly powerful, if they are based on von Neumann type architectures, they will consume between 20 and 30 megawatts of power and will not have intrinsic physically built-in capabilities to learn or deal with complex data as our brain does. These needs can be addressed by neuromorphic computing systems which are inspired by the biological concepts of the human brain. This new generation of computers has the potential to be used for the storage and processing of large amounts of digital information with much lower power consumption than conventional processors. Among their potential future applications, an important niche is moving the control from data centers to edge devices. The aim of this roadmap is to present a snapshot of the present state of neuromorphic technology and provide an opinion on the challenges and opportunities that the future holds in the major areas of neuromorphic technology, namely materials, devices, neuromorphic circuits, neuromorphic algorithms, applications, and ethics. The roadmap is a collection of perspectives where leading researchers in the neuromorphic community provide their own view about the current state and the future challenges for each research area. We hope that this roadmap will be a useful resource by providing a concise yet comprehensive introduction to readers outside this field, for those who are just entering the field, as well as providing future perspectives for those who are well established in the neuromorphic computing community
IMAC-Sim: A Circuit-level Simulator For In-Memory Analog Computing Architectures
With the increased attention to memristive-based in-memory analog computing
(IMAC) architectures as an alternative for energy-hungry computer systems for
machine learning applications, a tool that enables exploring their device- and
circuit-level design space can significantly boost the research and development
in this area. Thus, in this paper, we develop IMAC-Sim, a circuit-level
simulator for the design space exploration of IMAC architectures. IMAC-Sim is a
Python-based simulation framework, which creates the SPICE netlist of the IMAC
circuit based on various device- and circuit-level hyperparameters selected by
the user, and automatically evaluates the accuracy, power consumption, and
latency of the developed circuit using a user-specified dataset. Moreover,
IMAC-Sim simulates the interconnect parasitic resistance and capacitance in the
IMAC architectures and is also equipped with horizontal and vertical
partitioning techniques to surmount these reliability challenges. IMAC-Sim is a
flexible tool that supports a broad range of device- and circuit-level
hyperparameters. In this paper, we perform controlled experiments to exhibit
some of the important capabilities of the IMAC-Sim, while the entirety of its
features is available for researchers via an open-source tool
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