1 research outputs found
High efficiency wide-band line drivers in low voltage CMOS using Class-D techniques
In this thesis, the applicability of Class-D amplifiers to integrated wide-band
communication line driver applications is studied. While Class-D techniques
can address some of the efficiency limitations of linear amplifier structures
and have shown promising results in low frequency applications, the low
frequency techniques and knowledge need further development in order to
improve their practicality for wide band systems.
New structures and techniques to extend the application of Class-D to
wide-band communication systems, in particular the HomePlug AV wire-
line communication standard, will be proposed. Additionally, the digital
processing requirements of these wide-band systems drives rapid movement
towards nanometer technology nodes and presents new challenges which will
be addressed, and new opportunities which will be exploited, for wide-band
integrated Class-D line drivers.
There are three main contributions of this research. First, a model of Class-D
efficiency degradation mechanisms is created, which allows the impact of
high-level design choices such as supply voltage, process technology and
operating frequency to be assessed. The outcome of this section is a strategy
for pushing the high efficiency of Class-D to wide band communication
applications, with switching frequencies up to many hundreds of Megahertz.
A second part of this research considers the design of efficient, fast and
high power Class-D output stages, as these are the major efficiency and
bandwidth bottleneck in wide-band applications. A novel NMOS-only totem
pole output stage with a fast, integrated drive structure will be proposed.
In a third section, a complete wide-band Class-D line driver is designed in a
0.13μm digital CMOS process. The line driver is systematically designed
using a rigorous development methodology and the aims are to maximise
the achievable signal bandwidth while minimising power dissipation. Novel
circuits and circuit structures are proposed as part of this section and the
resulting fabricated Class-D line driver test chip shows an efficiency of 15%
while driving a 30MHz wide signal with an MTPR of 22dB, at 33mW injected
power