Noise-Adaptive Compiler Mappings for Noisy Intermediate-Scale Quantum Computers

A massive gap exists between current quantum computing (QC) prototypes, and the size and scale required for many proposed QC algorithms. Current QC implementations are prone to noise and variability which affect their reliability, and yet with less than 80 quantum bits (qubits) total, they are too resource-constrained to implement error correction. The term Noisy Intermediate-Scale Quantum (NISQ) refers to these current and near-term systems of 1000 qubits or less. Given NISQ's severe resource constraints, low reliability, and high variability in physical characteristics such as coherence time or error rates, it is of pressing importance to map computations onto them in ways that use resources efficiently and maximize the likelihood of successful runs. This paper proposes and evaluates backend compiler approaches to map and optimize high-level QC programs to execute with high reliability on NISQ systems with diverse hardware characteristics. Our techniques all start from an LLVM intermediate representation of the quantum program (such as would be generated from high-level QC languages like Scaffold) and generate QC executables runnable on the IBM Q public QC machine. We then use this framework to implement and evaluate several optimal and heuristic mapping methods. These methods vary in how they account for the availability of dynamic machine calibration data, the relative importance of various noise parameters, the different possible routing strategies, and the relative importance of compile-time scalability versus runtime success. Using real-system measurements, we show that fine grained spatial and temporal variations in hardware parameters can be exploited to obtain an average $2.9$x (and up to $18$x) improvement in program success rate over the industry standard IBM Qiskit compiler.Comment: To appear in ASPLOS'1

A Language and Hardware Independent Approach to Quantum-Classical Computing

Heterogeneous high-performance computing (HPC) systems offer novel architectures which accelerate specific workloads through judicious use of specialized coprocessors. A promising architectural approach for future scientific computations is provided by heterogeneous HPC systems integrating quantum processing units (QPUs). To this end, we present XACC (eXtreme-scale ACCelerator) --- a programming model and software framework that enables quantum acceleration within standard or HPC software workflows. XACC follows a coprocessor machine model that is independent of the underlying quantum computing hardware, thereby enabling quantum programs to be defined and executed on a variety of QPUs types through a unified application programming interface. Moreover, XACC defines a polymorphic low-level intermediate representation, and an extensible compiler frontend that enables language independent quantum programming, thus promoting integration and interoperability across the quantum programming landscape. In this work we define the software architecture enabling our hardware and language independent approach, and demonstrate its usefulness across a range of quantum computing models through illustrative examples involving the compilation and execution of gate and annealing-based quantum programs

The Coherent Parity Check Framework for Quantum Error Correction

Quantum error correction protocols are an essential element in the design of any circuit-model quantum computer. In this thesis, I introduce the coherent parity check (CPC) framework for quantum error correction. CPC codes have a fundamental structure in which quantum parity check measurements are stored coherently and compared over time. The specific advantage of the CPC code structure is that it provides a way of creating new stabilizer codes from the starting point of any sequence of parity checks. I show that this freedom in the choice of parity checks can be used to derive methods for the construction of distance-three quantum codes based on almost any distance-three classical code. The CPC framework has further applications in machine search routines for code discovery, as well as in the design of bespoke codes tailored for the demands of a given device. Another feature of CPC codes is that they can be represented as factor graphs of the type commonly seen in classical error correction and machine learning. I outline a procedure for this mapping, and demonstrate how a quantum code can be derived by manipulating its factor graph representation. The aim of the factor graph mapping for CPC codes is to make it easier to adapt well-developed techniques from classical information theory for use with quantum codes. This will make the CPC framework a useful tool for the theoretical and practical study of quantum error correction codes as large-scale quantum computers move closer to becoming a reality

Signal processing techniques for efficient compilation of controlled rotations in trapped ions

Quantum logic gates with many control qubits are essential in many quantum algorithms, but remain challenging to perform in current experiments. Trapped ion quantum computers natively feature a different type of entangling operation, namely the Molmer-Sorensen (MS) gate which effectively applies an Ising interaction to all qubits at the same time. We consider a sequence of equal all-to-all MS operations, interleaved with single qubit gates that act only on one special qubit. Using a connection with quantum signal processing techniques, we find that it is possible to perform an arbitray SU(2) rotation on the special qubit if and only if all other qubits are in the state |1>. Such controlled rotation gates with N-1 control qubits require 2N applications of the MS gate, and can be mapped to a conventional Toffoli gate by demoting a single qubit to ancilla.Comment: 14 pages, 3 figures, comments welcome. v3 includes several fixes and adds an appendix with explicit angle

t|ket> : A retargetable compiler for NISQ devices

We present t|ket>, a quantum software development platform produced by Cambridge Quantum Computing Ltd. The heart of t|ket> is a language-agnostic optimising compiler designed to generate code for a variety of NISQ devices, which has several features designed to minimise the influence of device error. The compiler has been extensively benchmarked and outperforms most competitors in terms of circuit optimisation and qubit routing