Noise shaping Asynchronous SAR ADC based time to digital converter

Time-to-digital converters (TDCs) are key elements for the digitization of timing information in modern mixed-signal circuits such as digital PLLs, DLLs, ADCs, and on-chip jitter-monitoring circuits. Especially, high-resolution TDCs are increasingly employed in on-chip timing tests, such as jitter and clock skew measurements, as advanced fabrication technologies allow fine on-chip time resolutions. Its main purpose is to quantize the time interval of a pulse signal or the time interval between the rising edges of two clock signals. Similarly to ADCs, the performance of TDCs are also primarily characterized by Resolution, Sampling Rate, FOM, SNDR, Dynamic Range and DNL/INL. This work proposes and demonstrates 2nd order noise shaping Asynchronous SAR ADC based TDC architecture with highest resolution of 0.25 ps among current state of art designs with respect to post-layout simulation results. This circuit is a combination of low power/High Resolution 2nd Order Noise Shaped Asynchronous SAR ADC backend with simple Time to Amplitude converter (TAC) front-end and is implemented in 40nm CMOS technology. Additionally, special emphasis is given on the discussion on various current state of art TDC architectures.Electrical and Computer Engineerin

Simulation-based high-level synthesis of Nyquist-rate data converters using MATLAB/SIMULINK

This paper presents a toolbox for the simulation, optimization and high-level synthesis of Nyquist-rate Analog-to-Digital (A/D) and Digital-to-Analog (D/A) Converters in MATLAB®. The embedded simulator uses SIMULINK® C-coded S-functions to model all required subcircuits including their main error mechanisms. This approach allows to drastically speed up the simulation CPU-time up to 2 orders of magnitude as compared with previous approaches - based on the use of SIMULINK® elementary blocks. Moreover, S-functions are more suitable for implementing a more detailed description of the circuit. For all subcircuits, the accuracy of the behavioral models has been verified by electrical simulation using HSPICE. For synthesis purposes, the simulator is used for performance evaluation and combined with an hybrid optimizer for design parameter selection. The optimizer combines adaptive statistical optimization algorithm inspired in simulated annealing with a design-oriented formulation of the cost function. It has been integrated in the MATLAB/SIMULINK® platform by using the MATLAB® engine library, so that the optimization core runs in background while MATLAB® acts as a computation engine. The implementation on the MATLAB® platform brings numerous advantages in terms of signal processing, high flexibility for tool expansion and simulation with other electronic subsystems. Additionally, the presented toolbox comprises a friendly graphical user interface to allow the designer to browse through all steps of the simulation, synthesis and post-processing of results. In order to illustrate the capabilities of the toolbox, a 0.13)im CMOS 12bit@80MS/s analog front-end for broadband power line communications, made up of a pipeline ADC and a current steering DAC, is synthesized and high-level sized. Different experiments show the effectiveness of the proposed methodology.Ministerio de Ciencia y Tecnología TIC2003-02355RAICONI

A 13-bit, 2.2-MS/s, 55-mW multibit cascade ΣΔ modulator in CMOS 0.7-μm single-poly technology

This paper presents a CMOS 0.7-μm ΣΔ modulator IC that achieves 13-bit dynamic range at 2.2 MS/s with an oversampling ratio of 16. It uses fully differential switched-capacitor circuits with a clock frequency of 35.2 MHz, and has a power consumption of 55 mW. Such a low oversampling ratio has been achieved through the combined usage of fourth-order filtering and multibit quantization. To guarantee stable operation for any input signal and/or initial condition, the fourth-order shaping function has been realized using a cascade architecture with three stages; the first stage is a second-order modulator, while the others are first-order modulators - referred to as a 2-1-1mb architecture. The quantizer of the last stage is 3 bits, while the other quantizers are single bit. The modulator architecture and coefficients have been optimized for reduced sensitivity to the errors in the 3-bit quantization process. Specifically, the 3-bit digital-to-analog converter tolerates 2.8% FS nonlinearity without significant degradation of the modulator performance. This makes the use of digital calibration unnecessary, which is a key point for reduced power consumption. We show that, for a given oversampling ratio and in the presence of 0.5% mismatch, the proposed modulator obtains a larger signal-to-noise-plus-distortion ratio than previous multibit cascade architectures. On the other hand, as compared to a 2-1-1single-bit modulator previously designed for a mixed-signal asymmetrical digital subscriber line modem in the same technology, the modulator in this paper obtains one more bit resolution, enhances the operating frequency by a factor of two, and reduces the power consumption by a factor of four.Comisión Interministerial de Ciencia y Tecnología TIC97-0580European Commission ESPRIT 879

Dynamic element matching techniques for data converters

Analog to digital converter (ADC) circuit component errors create nonuniform quantization code widths and create harmonic distortion in an ADC\u27s output. In this dissertation, two techniques for estimating an ADC\u27s output spectrum from the ADC\u27s transfer function are determined. These methods are compared to a symmetric power function and asymmetric power function approximations. Standard ADC performance metrics, such as SDR, SNDR, SNR, and SFDR, are also determined as a function of the ADC\u27s transfer function approximations. New dynamic element matching (DEM) flash ADCs are developed. An analysis of these DEM flash ADCs is developed and shows that these DEM algorithms improve an ADC\u27s performance. The analysis is also used to analyze several existing DEM ADC architectures; Digital to analog converter (DAC) circuit component errors create nonuniform quantization code widths and create harmonic distortion in a DAC\u27s output. In this dissertation, an exact relationship between a DAC\u27s integral nonlinearity (INL) and its output spectrum is determined. Using this relationship, standard DAC performance metrics, such as SDR, SNDR, SNR, and SFDR, are calculated from the DAC\u27s transfer function. Furthermore, an iterative method is developed which determines an arbitrary DAC\u27s transfer function from observed output magnitude spectra. An analysis of DEM techniques for DACs, including the determination of several suitable metrics by which DEM techniques can be compared, is derived. The performance of a given DEM technique is related to standard DAC performance metrics, such as SDR, SNDR, and SFDR. Conditions under which DEM techniques can guarantee zero average INL and render the distortion due to mismatched components as white noise are developed. Several DEM circuits proposed in the literature are shown to be equivalent and have hardware efficient implementations based on multistage interconnection networks. Example DEM circuit topologies and their hardware efficient VLSI implementations are also presented

Digital Background Self-Calibration Technique for Compensating Transition Offsets in Reference-less Flash ADCs

This Dissertation focusses on proving that background calibration using adaptive algorithms are low-cost, stable and effective methods for obtaining high accuracy in flash A/D converters. An integrated reference-less 3-bit flash ADC circuit has been successfully designed and taped out in UMC 180 nm CMOS technology in order to prove the efficiency of our proposed background calibration. References for ADC transitions have been virtually implemented built-in in the comparators dynamic-latch topology by a controlled mismatch added to each comparator input front-end. An external very simple DAC block (calibration bank) allows control the quantity of mismatch added in each comparator front-end and, therefore, compensate the offset of its effective transition with respect to the nominal value. In order to assist to the estimation of the offset of the prototype comparators, an auxiliary A/D converter with higher resolution and lower conversion speed than the flash ADC is used: a 6-bit capacitive-DAC SAR type. Special care in synchronization of analogue sampling instant in both ADCs has been taken into account. In this thesis, a criterion to identify the optimum parameters of the flash ADC design with adaptive background calibration has been set. With this criterion, the best choice for dynamic latch architecture, calibration bank resolution and flash ADC resolution are selected. The performance of the calibration algorithm have been tested, providing great programmability to the digital processor that implements the algorithm, allowing to choose the algorithm limits, accuracy and quantization errors in the arithmetic. Further, systematic controlled offset can be forced in the comparators of the flash ADC in order to have a more exhaustive test of calibration

Low harmonic distortion flash A/D converters incorporating dynamic element matching techniques

New dynamic element matching techniques are shown to reduce the harmonic distortion and improve the spurious-free dynamic range of flash ADCs. Resistor chain mismatch errors are negated by randomly rearranging the resistors each sample by utilizing 5(2{dollar}\sp{b}{dollar}-1) digital switches and b + 1 random control signals for a b-bit flash ADC. The integral and differential nonlinearity of a non-ideal flash ADC are derived for three common resistor chain mismatch errors; namely, geometric mismatches, linear gradient mismatches, and dynamic mismatches. The transfer function of a non-ideal flash ADC is also derived and the converter output is shown to consist of a scaled copy of the input, a DC gain, and conversion noise that is a function of the resistor mismatches. A comprehensive summary of dynamic element matching techniques given in literature is provided. In addition, the DEM network introduced by Galton and Jensen is shown to be equivalent to the generalized-cube network used in parallel processing architectures. An alternative version of this network that uses logic gates is also proposed

Calibration techniques in nyquist A/D converters

In modern systems signal processing is performed in the digital domain. Contrary to analog circuits, digital signal processing offers more robustness, programmability, error correction and storage possibility. The trend to shift the A/D converter towards the input of the system requires A/D converters with more dynamic range and higher sampling speeds. This puts extreme demands on the A/D converter and potentially increases the power consumption. Calibration Techniques in Nyquist A/D Converters analyses different A/D-converter architectures with an emphasis on the maximum achievable power efficiency. It is shown that in order to achieve high speed and high accuracy at high power efficiency, calibration is required. Calibration reduces the overall power consumption by using the available digital processing capability to relax the demands on critical power hungry analog components. Several calibration techniques are analyzed. The calibration techniques presented in this book are applicable to other analog-to-digital systems, such as those applied in integrated receivers. Further refinements will allow using analog components with less accuracy, which will then be compensated by digital signal processing. The presented methods allow implementing this without introducing a speed or power penalty

Precise linear signal generation with nonideal components and deterministic dynamic element matching

A dynamic element matching (DEM) approach to ADC testing is introduced. Two variants of this method are introduced and compared; a deterministic DEM method and a random DEM method. With both variants, a highly non-ideal DAC is used to generate an excitation for a DUT that has effective linearity that far exceeds that of the DAC. Simulation results show that both methods can be used for testing of ADCs. The deterministic DEM (DDEM) offers potential for a substantial reduction in the number of samples when compared with a random DEM approach with the same measurement accuracy. It is shown that the concept of usinf DEM for signal generation in a test environment finds applications well-beyond ADC testing. The DDEM approach offers potential for use in both production test and BIST environments

A jittered-sampling correction technique for ADCs

In Analogue to Digital Converters (ADCs) jittered sampling raises the noise floor; this leads to a decrease in its Signal to Noise ratio (SNR) and its effective number of bits (ENOB). This research studies a technique that compensate for the effects of sampling with a jittered clock. A thorough understanding of sampling in various data converters is complied