3 research outputs found
Power supply noise and logic error probability
Voltage fluctuations caused by parasitic impedances in the power supply rails of modern ICs are a major concern in nowadays ICs. The voltage fluctuations are spread out to the diverse nodes of the internal sections causing two effects: a degradation of performances mainly impacting gate delays and
a noisy contamination of the quiescent levels of the logic that drives the node. Both effects are presented together, in this
paper, showing than both are a cause of errors in modern and future digital circuits. The paper groups both error mechanisms
and shows how the global error rate is related with the voltage deviation and the period of the clock of the digital system.Peer Reviewe
Error probability in synchronous digital circuits due to power supply noise
This paper presents a probabilistic approach to model the problem of power supply voltage fluctuations. Error probability calculations are shown for some 90-nm technology digital circuits.
The analysis here considered gives the timing violation error probability as a new design quality factor in front of conventional techniques that assume the full perfection of the circuit. The evaluation of the error bound can be useful for new design paradigms where retry and self-recovering
techniques are being applied to the design of high performance processors. The method here described allows to evaluate the performance of these techniques by means of calculating the expected error probability in terms of power supply distribution quality.Peer Reviewe
Error probability in synchronous digital circuits due to power supply noise
This paper presents a probabilistic approach to model
the problem of power supply voltage fluctuations. Error
probability calculations are shown for some 90-nm technology
digital circuits. The analysis here considered gives the
timing violation error probability as a new design quality
factor in front of conventional techniques that assume the
full perfection of the circuit. The evaluation of the error
bound can be useful for new design paradigms where retry
and self-recovering techniques are being applied to the design
of high performance processors. The method here described
allows to evaluate the performance of these techniques
by means of calculating the expected error probability
in terms of power supply distribution quality.Postprint (published version