2 research outputs found
PALS: Distributed Gradient Clocking on Chip
Consider an arbitrary network of communicating modules on a chip, each
requiring a local signal telling it when to execute a computational step. There
are three common solutions to generating such a local clock signal: (i) by
deriving it from a single, central clock source, (ii) by local, free-running
oscillators, or (iii) by handshaking between neighboring modules. Conceptually,
each of these solutions is the result of a perceived dichotomy in which
(sub)systems are either clocked or asynchronous. We present a solution and its
implementation that lies between these extremes. Based on a distributed
gradient clock synchronization algorithm, we show a novel design providing
modules with local clocks, the frequency bounds of which are almost as good as
those of free-running oscillators, yet neighboring modules are guaranteed to
have a phase offset substantially smaller than one clock cycle. Concretely,
parameters obtained from a 15nm ASIC simulation running at 2GHz yield
mathematical worst-case bounds of 20ps on the phase offset for a
node grid network
Custom Cell Placement Automation for Asynchronous VLSI
Asynchronous Very-Large-Scale-Integration (VLSI) integrated circuits have demonstrated many advantages over their synchronous counterparts, including low power consumption, elastic pipelining, robustness against manufacturing and temperature variations, etc. However, the lack of dedicated electronic design automation (EDA) tools, especially physical layout automation tools, largely limits the adoption of asynchronous circuits. Existing commercial placement tools are optimized for synchronous circuits, and require a standard cell library provided by semiconductor foundries to complete the physical design. The physical layouts of cells in this library have the same height to simplify the placement problem and the power distribution network. Although the standard cell methodology also works for asynchronous designs, the performance is inferior compared with counterparts designed using the full-custom design methodology. To tackle this challenge, we propose a gridded cell layout methodology for asynchronous circuits, in which the cell height and cell width can be any integer multiple of two grid values. The gridded cell approach combines the shape regularity of standard cells with the size flexibility of full-custom layouts. Therefore, this approach can achieve a better space utilization ratio and lower wire length for asynchronous designs. Experiments have shown that the gridded cell placement approach reduces area without impacting the routability. We have also used this placer to tape out a chip in a 65nm process technology, demonstrating that our placer generates design-rule clean results