Unifying mesh- and tree-based programmable interconnect

We examine the traditional, symmetric, Manhattan mesh design for field-programmable gate-array (FPGA) routing along with tree-of-meshes (ToM) and mesh-of-trees (MoT) based designs. All three networks can provide general routing for limited bisection designs (Rent's rule with p<1) and allow locality exploitation. They differ in their detailed topology and use of hierarchy. We show that all three have the same asymptotic wiring requirements. We bound this tightly by providing constructive mappings between routes in one network and routes in another. For example, we show that a (c,p) MoT design can be mapped to a (2c,p) linear population ToM and introduce a corner turn scheme which will make it possible to perform the reverse mapping from any (c,p) linear population ToM to a (2c,p) MoT augmented with a particular set of corner turn switches. One consequence of this latter mapping is a multilayer layout strategy for N-node, linear population ToM designs that requires only /spl Theta/(N) two-dimensional area for any p when given sufficient wiring layers. We further show upper and lower bounds for global mesh routes based on recursive bisection width and show these are within a constant factor of each other and within a constant factor of MoT and ToM layout area. In the process we identify the parameters and characteristics which make the networks different, making it clear there is a unified design continuum in which these networks are simply particular regions

Some results on FPGAs, file transfers, and factorizations of graphs.

by Pan Jiao Feng.Thesis (M.Phil.)--Chinese University of Hong Kong, 1998.Includes bibliographical references (leaves 89-93).Abstract also in Chinese.Abstract --- p.iAcknowledgments --- p.vList of Tables --- p.xList of Figures --- p.xiChapter Chapter 1. --- Introduction --- p.1Chapter 1.1 --- Graph definitions --- p.2Chapter 1.2 --- The S box graph --- p.2Chapter 1.3 --- The file transfer graph --- p.4Chapter 1.4 --- "(g, f)-factor and (g, f)-factorization" --- p.5Chapter 1.5 --- Thesis contributions --- p.6Chapter 1.6 --- Organization of the thesis --- p.7Chapter Chapter 2. --- On the Optimal Four-way Switch Box Routing Structures of FPGA Greedy Routing Architectures --- p.8Chapter 2.1 --- Introduction --- p.9Chapter 2.1.1 --- FPGA model and S box model --- p.9Chapter 2.1.2 --- FPGA routing --- p.10Chapter 2.1.3 --- Problem formulation --- p.10Chapter 2.2 --- Definitions and terminology --- p.12Chapter 2.2.1 --- General terminology --- p.12Chapter 2.2.2 --- Graph definitions --- p.15Chapter 2.2.3 --- The S box graph --- p.15Chapter 2.3 --- Properties of the S box graph and side-to-side graphs --- p.16Chapter 2.3.1 --- On the properties of the S box graph --- p.16Chapter 2.3.2 --- The properties of side-to-side graphs --- p.19Chapter 2.4 --- Conversion of the four-way FPGA routing problem --- p.23Chapter 2.4.1 --- Conversion of the S box model --- p.24Chapter 2.4.2 --- Conversion of the DAAA model --- p.26Chapter 2.4.3 --- Conversion of the DADA model --- p.27Chapter 2.4.4 --- Conversion of the DDDA model --- p.28Chapter 2.5 --- Low bounds of routing switches --- p.28Chapter 2.5.1 --- The lower bound of the DAAA model --- p.29Chapter 2.5.2 --- The lower bound of the DADA model --- p.30Chapter 2.5.3 --- The lower bound of the DDDA model --- p.31Chapter 2.6 --- Optimal structure of one-side predetermined four-way FPGA routing --- p.32Chapter 2.7 --- Optimal structures of two-side and three-side predetermined four-way FPGA routing --- p.45Chapter 2.7.1 --- Optimal structure of two-side predetermined four-way FPGA routing --- p.46Chapter 2.7.2 --- Optimal structure of three-side predetermined four-way FPGA routing --- p.47Chapter 2.8 --- Conclusion --- p.49Appendix --- p.50Chapter Chapter 3. --- "Application of (0, f)-Factorization on the Scheduling of File Transfers" --- p.53Chapter 3.1 --- Introduction --- p.53Chapter 3.1.1 --- "(0,f)-factorization" --- p.54Chapter 3.1.2 --- File transfer model and its graph --- p.54Chapter 3.1.3 --- Previous results --- p.56Chapter 3.1.4 --- Our results and outline of the chapter --- p.56Chapter 3.2 --- NP-completeness --- p.57Chapter 3.3 --- Some lemmas --- p.58Chapter 3.4 --- Bounds of file transfer graphs --- p.59Chapter 3.5 --- Comparison --- p.62Chapter 3.6 --- Conclusion --- p.68Chapter Chapter 4. --- "Decomposition Graphs into (g,f)-Factors" --- p.69Chapter 4.1 --- Introduction --- p.69Chapter 4.1.1 --- "(g,f)-factors and (g,f)-factorizations" --- p.69Chapter 4.1.2 --- Previous work --- p.70Chapter 4.1.3 --- Our results --- p.72Chapter 4.2 --- Proof of Theorem 2 --- p.73Chapter 4.3 --- Proof of Theorem 3 --- p.79Chapter 4.4 --- Proof of Theorem 4 --- p.80Chapter 4.5 --- Related previous results --- p.82Chapter 4.6 --- Conclusion --- p.84Chapter Chapter 5. --- Conclusion --- p.85Chapter 5.1 --- About graph-based approaches --- p.85Chapter 5.2 --- FPGA routing --- p.87Chapter 5.3 --- The scheduling of file transfer --- p.88Bibliography --- p.89Vita --- p.9