10,197 research outputs found
A Survey of Techniques For Improving Energy Efficiency in Embedded Computing Systems
Recent technological advances have greatly improved the performance and
features of embedded systems. With the number of just mobile devices now
reaching nearly equal to the population of earth, embedded systems have truly
become ubiquitous. These trends, however, have also made the task of managing
their power consumption extremely challenging. In recent years, several
techniques have been proposed to address this issue. In this paper, we survey
the techniques for managing power consumption of embedded systems. We discuss
the need of power management and provide a classification of the techniques on
several important parameters to highlight their similarities and differences.
This paper is intended to help the researchers and application-developers in
gaining insights into the working of power management techniques and designing
even more efficient high-performance embedded systems of tomorrow
EVEREST IST - 2002 - 00185 : D23 : final report
Deliverable pĂşblic del projecte europeu EVERESTThis deliverable constitutes the final report of the project IST-2002-001858 EVEREST. After its successful completion, the project presents this document that firstly summarizes the context, goal and the approach objective of the project. Then it presents a concise summary of the major goals and results, as well as highlights the most valuable lessons derived form the project work. A list of deliverables and publications is included in the annex.Postprint (published version
Low Power Processor Architectures and Contemporary Techniques for Power Optimization – A Review
The technological evolution has increased the number of transistors for a given die area significantly and increased the switching speed from few MHz to GHz range. Such inversely proportional decline in size and boost in performance consequently demands shrinking of supply voltage and effective power dissipation in chips with millions of transistors. This has triggered substantial amount of research in power reduction techniques into almost every aspect of the chip and particularly the processor cores contained in the chip. This paper presents an overview of techniques for achieving the power efficiency mainly at the processor core level but also visits related domains such as buses and memories. There are various processor parameters and features such as supply voltage, clock frequency, cache and pipelining which can be optimized to reduce the power consumption of the processor. This paper discusses various ways in which these parameters can be optimized. Also, emerging power efficient processor architectures are overviewed and research activities are discussed which should help reader identify how these factors in a processor contribute to power consumption. Some of these concepts have been already established whereas others are still active research areas. © 2009 ACADEMY PUBLISHER
Wrong-Path-Aware Entangling Instruction Prefetcher
© 2023.IEEE. This document is made available under the CC-BY 4.0 license http://creativecommons.org/licenses/by /4.0/
This document is the Accepted version of a Published Work that appeared in final form in IEEE Transactions on Computers. To access the final edited and published work see DOI 10.1109/TC.2023.3337308Instruction prefetching is instrumental for guaranteeing a high flow of instructions through the processor front
end for applications whose working set does not fit in the lowerlevel caches. Examples of such applications are server workloads,
whose instruction footprints are constantly growing. There are
two main techniques to mitigate this problem: fetch directed
prefetching (or decoupled front end) and instruction cache (L1I)
prefetching.
This work extends the state-of-the-art Entangling prefetcher
to avoid training during wrong-path execution. Our Entangling
wrong-path-aware prefetcher is equipped with microarchitectural
techniques that eliminate more than 99% of wrong-path pollution, thus reaching 98.9% of the performance of an ideal wrongpath-aware solution. Next, we propose two microarchitectural
optimizations able to further increase performance benefits by
1.8%, on average. All this is achieved with just 304 bytes.
Finally, we study the interplay between the L1I prefetcher and
a decoupled front end. Our analysis shows that due to pollution
caused by wrong-path instructions, the degree of decoupling
cannot be increased unlimitedly without negative effects on
the energy-delay product (EDP). Furthermore, the closer to
ideal is the L1I prefetcher, the less decoupling is required. For
example, our Entangling prefetcher reaches an optimal EDP with
a decoupling degree of 64 instructions
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