Architectures for soft-decision decoding of non-binary codes

En esta tesis se estudia el dise¿no de decodificadores no-binarios para la correcci'on de errores en sistemas de comunicaci'on modernos de alta velocidad. El objetivo es proponer soluciones de baja complejidad para los algoritmos de decodificaci'on basados en los c'odigos de comprobaci'on de paridad de baja densidad no-binarios (NB-LDPC) y en los c'odigos Reed-Solomon, con la finalidad de implementar arquitecturas hardware eficientes. En la primera parte de la tesis se analizan los cuellos de botella existentes en los algoritmos y en las arquitecturas de decodificadores NB-LDPC y se proponen soluciones de baja complejidad y de alta velocidad basadas en el volteo de s'¿mbolos. En primer lugar, se estudian las soluciones basadas en actualizaci'on por inundaci 'on con el objetivo de obtener la mayor velocidad posible sin tener en cuenta la ganancia de codificaci'on. Se proponen dos decodificadores diferentes basados en clipping y t'ecnicas de bloqueo, sin embargo, la frecuencia m'axima est'a limitada debido a un exceso de cableado. Por este motivo, se exploran algunos m'etodos para reducir los problemas de rutado en c'odigos NB-LDPC. Como soluci'on se propone una arquitectura basada en difusi'on parcial para algoritmos de volteo de s'¿mbolos que mitiga la congesti'on por rutado. Como las soluciones de actualizaci 'on por inundaci'on de mayor velocidad son sub-'optimas desde el punto de vista de capacidad de correci'on, decidimos dise¿nar soluciones para la actualizaci'on serie, con el objetivo de alcanzar una mayor velocidad manteniendo la ganancia de codificaci'on de los algoritmos originales de volteo de s'¿mbolo. Se presentan dos algoritmos y arquitecturas de actualizaci'on serie, reduciendo el 'area y aumentando de la velocidad m'axima alcanzable. Por 'ultimo, se generalizan los algoritmos de volteo de s'¿mbolo y se muestra como algunos casos particulares puede lograr una ganancia de codificaci'on cercana a los algoritmos Min-sum y Min-max con una menor complejidad. Tambi'en se propone una arquitectura eficiente, que muestra que el 'area se reduce a la mitad en comparaci'on con una soluci'on de mapeo directo. En la segunda parte de la tesis, se comparan algoritmos de decodificaci'on Reed- Solomon basados en decisi'on blanda, concluyendo que el algoritmo de baja complejidad Chase (LCC) es la soluci'on m'as eficiente si la alta velocidad es el objetivo principal. Sin embargo, los esquemas LCC se basan en la interpolaci'on, que introduce algunas limitaciones hardware debido a su complejidad. Con el fin de reducir la complejidad sin modificar la capacidad de correcci'on, se propone un esquema de decisi'on blanda para LCC basado en algoritmos de decisi'on dura. Por 'ultimo se dise¿na una arquitectura eficiente para este nuevo esquemaGarcía Herrero, FM. (2013). Architectures for soft-decision decoding of non-binary codes [Tesis doctoral no publicada]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/33753TESISPremiad

High speed RS(255, 239) decoder based on LCC decoding

Algebraic Soft-Decision Decoding (ASD) of Reed-Solomon (RS) codes provides higher coding gain over the conventional hard-decision decoding (HDD), but involves high computational complexity. Among the existing ASD methods, the Low Complexity Chase (LCC) decoding is the one with the lowest implementation cost. LCC decoding is based on generating 2 ¿ test vectors, where ¿ symbols are selected as the least reliable symbols for which hard-decision or the second more reliable decision are employed. Previous decoding algorithms for LCC decoders are based on interpolation and re-encoding techniques. On the other hand, HDD algorithms such as the Berlekamp-Massey (BM) algorithm or the Euclidean algorithm, despite of their low computational complexity, are not considered suitable for LCC decoding. In this paper, we present a new approach to LCC decoding based on one of these HDD algorithms, the inversion-less Berlekamp-Massey (iBM) algorithm, where the test vectors are selected for correction during decoding on occurrence of hard-decision decoding failure. The proposed architecture when applied to a RS(255, 239) code with ¿=3, saves a 20.5% and 2% of area compared to the LCC with factorization and a factorization-free decoder, respectively. In both cases, the latency is reduced by 34.5%, which is an increase of throughput rate in the same percentage since the critical path is the same in all the competing architectures. So an efficiency of at least 56% in terms of area-delay product can be obtained, compared with previous works. A complete RS(255, 239) LCC decoder with ¿=3 has been coded in VHDL and synthesized for implementation in Vitex-5 FPGA device, and by using SAED 90 nm standard cell library as well, and find a decoding rate of 710 Mbps and 4.2 Gbps and area of 2527 slices and 0.36 mm 2, respectively. © 2011 Springer Science+Business Media, LLC.This research was supported by FEDER and the Spanish Ministerio de Ciencia e Innovacion, under Grant No. TEC2008-06787.García Herrero, FM.; Valls Coquillat, J.; Meher, PK. (2011). High speed RS(255, 239) decoder based on LCC decoding. Circuits, Systems, and Signal Processing. 30(6):1643-1669. https://doi.org/10.1007/s00034-011-9327-4S16431669306J. Bellorado, Low-complexity soft decoding algorithms for Reed–Solomon codes. Ph.D. thesis, Harvard University, 2006D. Chase, A class of algorithms for decoding block codes with channel measurement information. IEEE Trans. Inf. Theory IT-18, 170–182 (1972)R.E. Blahut, Theory and Practice of Error-Control Codes (Addison-Wesley, Reading, 1983)R.E. Blahut, Algebraic Codes on Lines, Planes, and Curves, An Engineering Approach (University of Illinois, Urbana-Champaign, 2008)L. Hanzo, T.H. Liew, B.L. Yeap, Turbo Coding Equalisation and Space-Time Coding (University of Southampton, UK, 2002)W.J. Gross, F.R. Kschischang, P. Gulak, Architecture and implementation of an interpolation processor for soft-decision Reed–Solomon decoding. IEEE Trans. Very Large Scale Integr. 15(3), 309–318 (2007)W.J. Gross, F.R. Kschischang, R. Koetter, P. Glenn Gulak, A VLSI architecture for interpolation-based in soft-decision list decoding of Reed–Solomon decoders. J. VLSI Signal Process. 39(1–2), 93–111 (2005)J. Jiang, K. Narayanan, Algebraic soft-decision decoding of Reed- Solomon codes using bit-level soft information. IEEE Trans. Inf. Theory 54(9), 3907–3928 (2008)T.K. Moon, Error Correction Coding: Mathematical Methods And Algorithms (Wiley, New Jersey, 2004)K. Lee, M. O’Sullivan, An interpolation algorithm using Grobner bases for soft-decision decoding of Reed–Solomon codes, in Proc. of IEEE International Symposium on Information Theory, pp. 2032–2036, Seattle, Washington, Jul. 2006 (2006)H. Lee, A high-speed low-complexity Reed–Solomon decoder for optical communications. IEEE Trans. Circuits Syst. II 52(8), 461–465 (2005)H. Lee, High-speed VLSI architecture for parallel Reed–Solomon decoder. IEEE Trans. Very Large Scale Integr. 11(2), 288–294 (2003)S.L. Shieh, S.G. Lee, W.H. Sheen, A low-latency decoder for punctured/shortened Reed–Solomon codes, in IEEE 16th International Symposium on Personal, Indoor and Mobile Radio Communications (2005)R. Nielsen, Decoding AG-codes beyond half the minimum distance, Ph.D. dissertation, Tech. Univ. Denmark, Copenhagen, 1998R. Roth, G. Ruckenstein, Efficient decoding of Reed–Solomon codes beyond half the minimum distance. IEEE Trans. Inf. Theory 46, 246–257 (2000)Seth Kavish, K.N. Viswajith, S. Srinivasan, V. Kamakoti, Ultra Folded High-Speed Architectures for Reed–Solomon Decoders, in 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID’06), pp. 517–520 (2006)B. Sklar, Digital Communications: Fundamentals and Applications (Prentice Hall, New York, 2001)I.S. Reed, M.T. Shih, T.K. Truong, VLSI design of inverse-free Berlekamp–Massey algorithm. Proc. Inst. Electr. Eng. 138, 295–298 (1991)Dilip V. Sarwate, Naresh R. Shanbhag, High-speed architectures for Reed–Solomon decoders. IEEE Trans. Very Large Scale Integr. 9(5), 641–655 (2001)B. Yuan, Z. Wang, L. Li, M. Gao, J. Sha, C. Zhang, Area-efficient Reed–Solomon decoder design for optical communications. IEEE Trans. Circuits Syst. II 56(6), 469–473 (2009)X. Zhang, J. Zhu, High-throughput interpolation architecture for algebraic soft-decision Reed–Solomon decoding. IEEE Trans. Circuits Syst. I 57(3), 581–591 (2010)X. Zhang, J. Zhu, Hardware complexities of algebraic soft-decision Reed–Solomon decoders and comparisons, Information Theory and Applications, 2010X. Zhang, High-speed VLSI architecture for low-complexity chase soft-decision Reed–Solomon decoding, in Proc. Information Theory and Applications Workshop, San Diego, CA, Feb. 2009 (2009)J. Zhu, X. Zhang, Efficient VLSI architecture for soft-decision decoding of Reed–Solomon codes. IEEE Trans. Circuits Syst. I, Regul. Pap. 55(10), 3050–3062 (2008)J. Zhu, X. Zhang, Z. Wang, Backward interpolation architecture for algebraic soft-decision Reed–Solomon decoding. IEEE Trans. Very Large Scale Integr. 17(11), 1602–1615 (2009)J. Zhu, X. Zhang, Factorization-free low-complexity chase soft-decision decoding of Reed–Solomon codes, in Proc. IEEE International Symposium on Circuits and Systems, pp. 2677–2680, 2009J. Zhu, X. Zhang, Efficient architecture for generalized minimum-distance decoder of Reed–Solomon codes, in Acoustics Speech and Signal Processing (ICASSP), pp. 1502–1505, 201