Architectural, system level and protocol level techniques for power optimization for networked embedded systems

Summary form only given. Dynamic power management (DPM) entails employing strategies that yield acceptable trade-off between power/energy usage and their performance penalties. These include heuristic shutdown policies, prediction-based shutdown policies, multiple voltage scaling and stochastic modeling based policy optimization. On the other hand, architectural techniques for power savings include application specific techniques for multi-media hardware systems, and generic techniques like clock gating, on-line profiling based monitoring and control etc. Other paradigms of architectures such as network on chip (NoCs) target power optimization as well. Protocol level power optimization methods include generic techniques employed in wireless standard protocols, as well as techniques specific to multi-media traffic. DPM strategies get increasingly sophisticated due to improved power manageability of hardware components. In this context, there is a positive feedback in action. Power management techniques show the potential for power savings, and this pushes hardware developers to support more advanced (finer grained and lower overhead) power management modes. In this tutorial, we provide an overview of three main issues in three segments, namely, architecture level, system level and protocol level techniques of power minimization and management, how they influence each other. However, we do not concentrate on low power VLSI technique

Nanopower CMOS transponders for UHF and microwave RFID systems

At first, we present an analysis and a discussion of the design options and tradeoffs for a passive microwave transponder. We derive a set of criteria for the optimization of the voltage multiplier, the power matching network and the backscatter modulator in order to optimize the operating range. In order to match the strictly power requirements, the communication protocol between transponder and reader has been chosen in a convenient way, in order to make the architecture of the passive transponder very simple and then ultra-low-power. From the circuital point of view, the digital section has been implemented in subthreshold CMOS logic with very low supply voltage and clock frequency. We present different solutions to supply power to the transponder, in order to keep the power consumption in the deep sub-µW regime and to drastically reduce the huge sensitivity of the subthreshold logic to temperature and process variations. Moreover, a low-voltage and low-power EEPROM in a standard CMOS process has been implemented. Finally, we have presented the implementation of the entire passive transponder, operating in the UHF or microwave frequency range