Analysis of the Convergence Process by EXIT Charts for Parallel Implementations of Turbo Decoders

International audienceIterative process is a general principle in decoding powerful FEC codes such as turbo codes. However, the mutual information exchange during the iterative process is not easy to analyze and to describe. A useful technique to help the designer is the EXtrinsic Information Transfer (EXIT) chart. Unfortunately, this method cannot be directly applied to the decoding convergence analysis if parallel processing has to be exploited for the design of turbo decoders. In this letter, an extension of the EXIT charts method is proposed in order to take into account the constraints introduced by parallel implementations. The corresponding analysis associated with Monte-Carlo simulations gives additional understanding of the convergence process for the design of parallel architectures dedicated to turbo decoding

On the Convergence Speed of Turbo Demodulation with Turbo Decoding

Iterative processing is widely adopted nowadays in modern wireless receivers for advanced channel codes like turbo and LDPC codes. Extension of this principle with an additional iterative feedback loop to the demapping function has proven to provide substantial error performance gain. However, the adoption of iterative demodulation with turbo decoding is constrained by the additional implied implementation complexity, heavily impacting latency and power consumption. In this paper, we analyze the convergence speed of these combined two iterative processes in order to determine the exact required number of iterations at each level. Extrinsic information transfer (EXIT) charts are used for a thorough analysis at different modulation orders and code rates. An original iteration scheduling is proposed reducing two demapping iterations with reasonable performance loss of less than 0.15 dB. Analyzing and normalizing the computational and memory access complexity, which directly impact latency and power consumption, demonstrates the considerable gains of the proposed scheduling and the promising contributions of the proposed analysis.Comment: Submitted to IEEE Transactions on Signal Processing on April 27, 201

Energy-efficient design and implementation of turbo codes for wireless sensor network

The objective of this thesis is to apply near Shannon limit Error-Correcting Codes (ECCs), particularly the turbo-like codes, to energy-constrained wireless devices, for the purpose of extending their lifetime. Conventionally, sophisticated ECCs are applied to applications, such as mobile telephone networks or satellite television networks, to facilitate long range and high throughput wireless communication. For low power applications, such as Wireless Sensor Networks (WSNs), these ECCs were considered due to their high decoder complexities. In particular, the energy efficiency of the sensor nodes in WSNs is one of the most important factors in their design. The processing energy consumption required by high complexity ECCs decoders is a significant drawback, which impacts upon the overall energy consumption of the system. However, as Integrated Circuit (IC) processing technology is scaled down, the processing energy consumed by hardware resources reduces exponentially. As a result, near Shannon limit ECCs have recently begun to be considered for use in WSNs to reduce the transmission energy consumption [1,2]. However, to ensure that the transmission energy consumption reduction granted by the employed ECC makes a positive improvement on the overall energy efficiency of the system, the processing energy consumption must still be carefully considered.The main subject of this thesis is to optimise the design of turbo codes at both an algorithmic and a hardware implementation level for WSN scenarios. The communication requirements of the target WSN applications, such as communication distance, channel throughput, network scale, transmission frequency, network topology, etc, are investigated. Those requirements are important factors for designing a channel coding system. Especially when energy resources are limited, the trade-off between the requirements placed on different parameters must be carefully considered, in order to minimise the overall energy consumption. Moreover, based on this investigation, the advantages of employing near Shannon limit ECCs in WSNs are discussed. Low complexity and energy-efficient hardware implementations of the ECC decoders are essential for the target applications

Turbo Multiuser Detection Architectures

The discovery of Turbo Codes in 1996 by Berrou et. al. proved to be a huge boost for the research of channel coding. The Turbo Principle behind turbo codes was found to be applicable in other areas. One of these areas is Multiuser Detection. In this thesis, Turbo Multiuser Detection is investigated in order to answer two main questions. The questions concern the performance gain that is obtained when turbo multiuser detection is used instead of non-turbo multiuser detection and the convergence behavior of turbo multiuser detection. The performance gain is determined by comparing the bit-error-rate (BER) chart of a turbo multiuser detection architecture with the BER chart of a non-turbo multiuser detector. It was found that turbo multiuser detection results in a dramatical performance gain when Eb/N0 > 3 dB and more than one iteration is performed. The convergence behavior of turbo multiuser detection is analyzed with the help of EXIT charts. EXIT charts are recently proposed by S. ten Brink as a tool to analyze the convergence behavior of turbo architectures. EXIT charts are discussed in this thesis. An EXIT chart of a turbo multiuser detection architecture is created. From this chart, the minimum number of iterations to obtain the lowest BER possible are found.\ud EXIT charts are also used to analyze the difference of iterating aposteriori and extrinsic information in a turbo architecture. The analysis shows that EXIT charts of a-posteriori information give results, which contradict the results of simulations on turbo architectures

Design of Fixed-Point Processing Based Turbo Codes Using Extrinsic Information Transfer Charts

The operand-width specifications in fixed-point hardware implementations of turbo code decoders is an important design issue, since this governs the trade-off between the decoder's performance and its complexity, cost, area and energy consumption. The investigation of this issue would be extremely time-consuming in the conventional approach, which relies upon Monte-Carlo simulation based Bit Error Ratio (BER) analysis. In this paper, we propose a generic design method, which uses EXtrinsic Information Transfer (EXIT) chart analysis to simplify this design process. Our method is not only an order of magnitude faster than the conventional Monte-Carlo simulation based approach, but also offers deeper insights into why performance degradations are imposed by insufficient operand-width specifications. The benefits of our generic method are demonstrated in the context of a turbo decoder, allowing accurate specifications to be obtained and compared to those suggested by previous works

Bit-by-bit iterative decoding expedites the convergence of Repeat Accumulate decoders

In this paper, we propose bit-by-bit iterative decoding for expediting the convergence of Repeat Accumulate (RA) decoders. In a conventional RA decoder, the repeat and accumulate component decoders are operated iteratively, in order to facilitate near-capacity communication. However, whenever one decoder is activated, the other is kept idle. The outputs of the active component decoder are stored until its operation is completed, whereupon the outputs are forwarded to the other decoder all at once and the activation of the decoders is swapped. The proposed bit-by-bit RA decoder expedites this process by allowing both component decoders to operate simultaneously, continuously exchanging outputs without buffering. We present both EXtrinsic Information Transfer (EXIT) charts and Bit Error Ratio (BER) results, which demonstrate that the proposed bit-by-bit RA decoder requires fewer decoding iterations to converge, at the cost of a slightly increased complexity per decoding iteration. Overall, we demonstrate that in a range of practical scenarios, the proposed bit-by-bit RA offers gains of up to 0.86 dB, without imposing any additional decoding complexity and without requiring any additional transmission-energy, -bandwidth or -duration

CONVERGENCE IMPROVEMENT OF ITERATIVE DECODERS

Iterative decoding techniques shaked the waters of the error correction and communications field in general. Their amazing compromise between complexity and performance offered much more freedom in code design and made highly complex codes, that were being considered undecodable until recently, part of almost any communication system. Nevertheless, iterative decoding is a sub-optimum decoding method and as such, it has attracted huge research interest. But the iterative decoder still hides many of its secrets, as it has not been possible yet to fully describe its behaviour and its cost function. This work presents the convergence problem of iterative decoding from various angles and explores methods for reducing any sub-optimalities on its operation. The decoding algorithms for both LDPC and turbo codes were investigated and aspects that contribute to convergence problems were identified. A new algorithm was proposed, capable of providing considerable coding gain in any iterative scheme. Moreover, it was shown that for some codes the proposed algorithm is sufficient to eliminate any sub-optimality and perform maximum likelihood decoding. Its performance and efficiency was compared to that of other convergence improvement schemes. Various conditions that can be considered critical to the outcome of the iterative decoder were also investigated and the decoding algorithm of LDPC codes was followed analytically to verify the experimental results