Passive Switched Capacitor RF Front Ends for Spectrum Sensing in Cognitive Radios

This paper explores passive switched capacitor based RF receiver front ends for spectrum sensing. Wideband spectrum sensors remain the most challenging block in the software defined radio hardware design. The use of passive switched capacitors provides a very low power signal conditioning front end that enables parallel digitization and software control and cognitive capabilities in the digital domain. In this paper, existing architectures are reviewed followed by a discussion of high speed passive switched capacitor designs. A passive analog FFT front end design is presented as an example analog conditioning circuit. Design methodology, modeling, and optimization techniques are outlined. Measurements are presented demonstrating a 5 GHz broadband front end that consumes only 4 mW power

Channelization Techniques For Wideband Radios

University of Minnesota Ph.D. dissertation. May 2017. Major: Electrical Engineering. Advisor: Ramesh Harjani. 1 computer file (PDF); x, 110 pages.From the very start of mobile communications, wireless data traffic volume and the number of applications have increased continuously and this continued increase will eventually necessitate the use of wider signal bandwidths by the fundamental constraints imposed by Shannon’s theorem. Additionally, the air channel is a common limited resource that is shared by all users and applications. While this limited wireless resource has mostly been pre-allocated, the utilization at any given time is often very low. For this environment, cognitive radio and carrier aggregation are potential solutions. Both cognitive radio and carrier aggregation require the processing of wideband signals unlike what is normally the focus of conventional narrow band receivers. This, in turn, makes it necessary to design receivers with a large BW and high dynamic range, and these conflicting requirements typically form the bottleneck in existing systems. Here, we discuss channelization techniques using an analog FFT (fast Fourier transform) to solve the bottleneck. First, a fully integrated hybrid filter bank ADC using an analog FFT is presented. The proposed structure enables the signals in each channel of a wideband system to be separately digitized using the full dynamic range of the ADC, so the small signals in wideband can benefit in terms of lowered quantization noise while accommodating large in-band signals. The prototype which is implemented in TSMC’s 40nm CMOS GP process with VGA gains ranging from 1 to 4 shows 90.4mW total power consumption for both the analog and digital sections. Second, analog polyphase-FFT technique is introduced. Polyphase-FFT allows for low power implementations of high performance multi-channel filter banks by utilizing computation sharing not unlike a standard FFT. Additionally, it enables a longer “effective window length” than is possible in a standard FFT. This characteristic breaks the trade-off between the main-lobe width and the side-lobe amplitudes in normal finite impulse response (FIR) filters. The 4-channel I/Q prototype is implemented in TSMC’s 65nm GP technology. The measured trans- fer function shows >38dB side-lobe suppression at 1GS/s operation. The average measured IIP3 is +25dBm differential power and the total integrated output noise is 208µVrms. The total power consumption for the polyphase-FFT filter bank (8- channels total) is 34.6mW (34.6pJ/conv)

Circuit Techniques for Multiple and Wideband Beamforming

University of Minnesota Ph.D. dissertation.June 2018. Major: Electrical Engineering. Advisor: Ramesh Harjani. 1 computer file (PDF); x, 102 pages.This thesis presents different architectures with regard to multiple beamforming and wideband phased array transceiver. Three different designs are implemented in TSMC 65nm RF CMOS to demonstrate different solutions. The design in this thesis have included major RF blocks in state-of-art wireless transceiver: RF receiver, local oscillator, and RF transmitter. First, a RF/analog FFT based four-channel four-beam receiver with progressive partial spatial ltering is proposed. This architecture is particularly well suited for MIMO systems where multiple beams are used to increase throughput. Like the FFT, the proposed architecture reuses computations for multi-beam systems. In particular, the proposed architecture redistributes the computations so as to maximize the reuse of the structure that already exist in a receiver chain. In many fashions the architecture is quite similar to a Butler matrix but unlike the Butler matrix it does not use large passive components at RF. Further, we exploit the normally occurring quadrature down-conversion process to implement the tap weights. In comparison to traditional MIMO architectures, that effectively duplicate each path, the distributed computations of this architecture provide partial spatial ltering before the final stage, improving interference rejection for the blocks between the LNA and the ADC. Additionally, because of the spatial ltering prior to the ADC, a single interferer only jams a single beam allowing for continued operation though at a lower combined throughput. The four-beam receiver core prototype in 65nm CMOS implements the basic FFT based architecture but does not include an LNA or extensive IF stages. This four-channel design consumes 56mW power and occupies an active area of 0:65mm2 excluding pads and test circuits. Second, a wideband phased array receiver architecture with simultaneous spectral and spatial filtering by sub-harmonic injection oscillators is presented. The design avoids using expensive delay elements by many conventional wideband phased array. Different from prior art of channelization which cannot solve beam-squinting issue among the sub-channels, we use sub-harmonic injection locking scheme, which make the center frequencies of all sub-channels point to the same spatial direction to overcome beam-squinting issue. The low frequency, low power and narrowband phase shifters are placed at LO in comparison to conventional way of placing delay elements or phase shifters in the signal path. This avoids receiver performance degradation from delay elements or phase shifters. The simultaneous spectral and spatial ltering dictates less ADC dynamic range requirement and further reduces power. The injection locking scheme reduces the phase noise contribution from the oscillators. The two-band prototype design realized in 65nm GP CMOS is centered at 9GHz, provides 4GHz instantaneous bandwidth, reduces beam-squinting by half, consumes 31.75mW/antenna and occupies 2.7mm2 of chip area. In the third work, a steerable RF/analog FFT based four-beam transmitter architecture is presented. This work is based on the idea of FFT based multiple beamforming in 1st work, but extended to the transmitter and make the all beams steerable. Due to the reciprocity between receiver and transmitter, decimation-in-frequency (DIF) FFT is utilized in the transmitter. All the beams are steered simultaneously by front-end phase shifters, while keep each of the beams is independent of the others. The steerability of FFT based multiple beamforming scheme makes this proposed prototype could tackle more complicated portable wireless environment. The first and second proposed architecture have been silicon veried, and the design of the third has been finished and ready for tapeout

A power-scalable variable-length analogue DFT processor for multi-standard wireless transceivers

In the Orthogonal Frequency-Division Multiplexing (OFDM) based transceivers, digital computation of the Discrete Fourier Transform (DFT) is a power hungry process. Reduction in the hardware cost and power consumption is possible by implementing the DFT processor with analogue circuits. This thesis presents the real-time recursive DFT processor. Previously, changing the transform length and scaling the power could only be performed by digital Fast Fourier Transform (FFT) processors. By using the real-time recursive DFT processor, the decimation filter is eliminated. Thus, further reduction in the hardware cost and power consumption of the multi-standard transceiver is achieved. The real-time recursive DFT processor was designed in 180 nm CMOS technology. Results of device mismatch analysis indicate that the 8-point recursive DFT processor has a yield of 97.5% for the BPSK modulated signal. For the QPSK modulated signal, however, yield of the 8-point recursive DFT processor is 8.9%. Moreover, doubling the transform length reduces the average dynamic range by 3dB. Accordingly, the 16-point recursive DFT processor has a yield of 43.4% for the BPSK modulated signal. Power consumption of the recursive DFT processor is about 1/6 of the power consumption of a previous analogue FFT processor

CIRCUITS AND ARCHITECTURE FOR BIO-INSPIRED AI ACCELERATORS

Technological advances in microelectronics envisioned through Moore’s law have led to powerful processors that can handle complex and computationally intensive tasks. Nonetheless, these advancements through technology scaling have come at an unfavorable cost of significantly larger power consumption, which has posed challenges for data processing centers and computers at scale. Moreover, with the emergence of mobile computing platforms constrained by power and bandwidth for distributed computing, the necessity for more energy-efficient scalable local processing has become more significant. Unconventional Compute-in-Memory architectures such as the analog winner-takes-all associative-memory and the Charge-Injection Device processor have been proposed as alternatives. Unconventional charge-based computation has been employed for neural network accelerators in the past, where impressive energy efficiency per operation has been attained in 1-bit vector-vector multiplications, and in recent work, multi-bit vector-vector multiplications. In the latter, computation was carried out by counting quanta of charge at the thermal noise limit, using packets of about 1000 electrons. These systems are neither analog nor digital in the traditional sense but employ mixed-signal circuits to count the packets of charge and hence we call them Quasi-Digital. By amortizing the energy costs of the mixed-signal encoding/decoding over compute-vectors with many elements, high energy efficiencies can be achieved. In this dissertation, I present a design framework for AI accelerators using scalable compute-in-memory architectures. On the device level, two primitive elements are designed and characterized as target computational technologies: (i) a multilevel non-volatile cell and (ii) a pseudo Dynamic Random-Access Memory (pseudo-DRAM) bit-cell. At the level of circuit description, compute-in-memory crossbars and mixed-signal circuits were designed, allowing seamless connectivity to digital controllers. At the level of data representation, both binary and stochastic-unary coding are used to compute Vector-Vector Multiplications (VMMs) at the array level. Finally, on the architectural level, two AI accelerator for data-center processing and edge computing are discussed. Both designs are scalable multi-core Systems-on-Chip (SoCs), where vector-processor arrays are tiled on a 2-layer Network-on-Chip (NoC), enabling neighbor communication and flexible compute vs. memory trade-off. General purpose Arm/RISCV co-processors provide adequate bootstrapping and system-housekeeping and a high-speed interface fabric facilitates Input/Output to main memory