Analysis and Design of a 0.6 V 2.2 mW 58.5-to-72.9 GHz Divide-by-4 Injection-Locked Frequency Divider With Harmonic Boosting

A locking-range enhancement technique is proposed for divide-by-4 injection-locked frequency dividers (ILFDs) at millimeter-wave frequencies. The working principle of the conventional divide-by-4 ILFDs is analyzed and verified with simulations to show that the limited locking range is mainly attributed to low efficiency of harmonic mixing. Based on the observation, an enhancement technique is developed by employing a properly-designed 4th-order LC tank to boost the 3rd-order harmonic tone at the output to increase the injection efficiency and thus the locking range. Implemented in a 65-nm CMOS process, a divide-by-4 ILFD prototype with the proposed harmonic boosting technique measures a locking range of 21.9% from 58.53 GHz to 72.92 GHz while consuming 2.2 mW from a 0.6 V supply, which corresponds to FoM of 6.54

Design of low-voltage power efficient frequency dividers in folded MOS current mode logic

In this paper we propose a methodology to design high-speed, power-efficient static frequency dividers based on the low-voltage Folded MOS Current Mode Logic (FMCML) approach. A modeling strategy to analyze the dependence of propagation delay and power consumption on the bias currents of the divide-by-2 (DIV2) cell is introduced. We demonstrate that the behavior of the FMCML DIV2 cell is different both from the one of the conventional MCML DFF (D-type Flip-Flop) and from FMCML DFF without a level shifter. Then an analytical strategy to optimize the divider in different design scenarios: maximum speed, minimum power-delay product (PDP) or minimum energy-delay product (EDP) is presented. The possibility to scale the bias currents through the divider stages without affecting the speed performance is also investigated. The proposed analytical approach allows to gain a deep insight into the circuit behavior and to comprehensively optimize the different design tradeoffs. The derived models and design guidelines are validated against transistor level simulations referring to a commercial 28nm FDSOI CMOS process. Different divide-by-8 circuits following different optimization strategies have been designed in the same 28nm CMOS technology showing the effectiveness of the proposed methodology