Placement techniques in automatic analog layout generation.

模擬電路版圖設計是一個非常複雜和耗時的過程。通常情況下，設計一個高質量的模擬電路版圖需要電子工程師花費幾週甚至更長的時間。模擬電路的電子特性對於電路的細節設計非常敏感，因此，減小電路中的失配現象成為模擬電路版圖設計中一個非常重要的課題。在本論文中，我們提出了一系列實際的佈局技術，來降低電路的失配並提高繞線的成功率。我們可以非常容易的將這些技術整合至一個完整的模擬佈局和佈線的工具中，此工具可以在幾分鐘內生成一個完整的、高質量的模擬電路版圖。同時，該版圖能夠通過設計規則驗證（DRC）和佈局與電路設計一致性檢測（LVS）。模擬結果顯示，它的電路性能能夠與達到甚至超出手工設計的電路版圖。我們的論文主要作出了以下兩方面貢獻。1. 平衡佈局：對於模擬電路中的電子元器件，如電容、電阻、晶體管等進行一維和二維的平衡佈局。電子工程師可以根據不同的設計需求，通過選擇不同的佈局參數來改變電路的佈局排列方式。同時，在模擬退火算法中，我們著重考慮了器件間的匹配以生成高質量的模擬電路佈局。2. 消除阻塞的電路佈局：在模擬電路設計中，我們期望盡量避免在電子元器件密度較高的區域進行繞線。因此，我們需要在電路佈局設計過程中在電子元器件間留有足夠的佈線空間。為達到這個目標，我們提出了更精確的阻塞估計方法和版圖拓展方法，使其能夠生成一個高質量、高繞線成功率的電路佈局結果。為了驗證生成的電路版圖的質量和匹配特性，我們利用蒙地卡羅方法來模擬電路中的製程偏差和失配特性。實驗結果顯示，我們的工具可以在幾分鐘內自動生成高質量的電路版圖，與人工設計通常需要花費數日至數週相比，設計時間大幅縮短，同時電路的匹配特性得以提升。Analog layout design is a complicated and time-consuming process. It often takes couples of weeks for the layout designers to generate a qualied layout. The elec-trical properties of analog circuit are very sensitive to the layout details, and mis-match reduction becomes a very important issue in analog layout design.In this thesis, we will present some practical placement techniques to reduce mismatch and improve routability. These techniques can be easily integrated into a complete analog placement and routing ow, which can produce in just a few min-utes a complete and high quality layout for analog circuits that passes the design rule check, layout-schematic check and with performance veried by simulations. The contents of this thesis will focus on the following two issues:(1) Symmetry Placement: We consider symmetric placement of transistors, re-sistors and capacitors, which includes 1-D symmetry and 2-D symmetry (or called common centroid). Different symmetric placement congurations, derived accord-ing to the practical needs in analog design, are considered for the matching devices in the simulated annealing engine of the placer in order to generate a placement with high quality.(2) Congestion-driven Placement: In analog design, wires are preferred not be routed over active devices, so we need to leave enough spaces properly for routing between the devices during the placement process. To achieve this, we explore congestion estimation and layout expansion during the placement step in order to produce a good and routable solution.In order to verify the quality of the generated layouts in terms of mismatch, we will run Monte Carlo simulations on them with variations in process and mismatch. Experiments show that our methodology can generate high quality layout automatically in just a few minutes while manual design may take couples of days.Detailed summary in vernacular field only.Detailed summary in vernacular field only.Detailed summary in vernacular field only.Detailed summary in vernacular field only.Detailed summary in vernacular field only.Cui, Guxin.Thesis (M.Phil.)--Chinese University of Hong Kong, 2012.Abstracts also in Chinese.Abstract --- p.iAcknowledgement --- p.ivChapter 1 --- Introduction --- p.1Chapter 1.1 --- Background --- p.1Chapter 1.2 --- Physical Design --- p.2Chapter 1.3 --- Analog Placement --- p.4Chapter 1.3.1 --- Methodologies of Analog Placement --- p.4Chapter 1.3.2 --- Symmetry Constraints of Analog Placement --- p.5Chapter 1.4 --- Process Variation and Layout Mismatch --- p.6Chapter 1.4.1 --- Process Variation --- p.6Chapter 1.4.2 --- Random Mismatch and Systematic Mismatch --- p.7Chapter 1.5 --- Monte Carlo Simulation Procedure --- p.9Chapter 1.6 --- Problem Formulation of Placement --- p.9Chapter 1.7 --- Motivations --- p.10Chapter 1.8 --- Contributions --- p.11Chapter 1.9 --- Thesis Organization --- p.12Chapter 2 --- Literature Review on Analog Placement --- p.13Chapter 2.1 --- Topological Representations Handling Symmetry Constraints --- p.14Chapter 2.1.1 --- Symmetry within the Sequence-Pair (SP) Representation . --- p.14Chapter 2.1.2 --- Block Placement with Symmetry Constraints Based on the O-Tree Non-Slicing Representation --- p.16Chapter 2.1.3 --- Placement with Symmetry Constraints for Analog Layout Design Using TCG-S --- p.17Chapter 2.1.4 --- Modeling Non-Slicing Floorplans with Binary Trees --- p.19Chapter 2.1.5 --- Segment Trees Handle Symmetry Constraints --- p.20Chapter 2.1.6 --- Center-based Corner Block List --- p.22Chapter 2.2 --- Other Works on Analog Placement Constraints --- p.25Chapter 2.2.1 --- Deterministic Analog Placement with Hierarchically Bounded Enumeration and Enhanced Shape Functions --- p.25Chapter 2.2.2 --- Analog Placement Based on Symmetry-Island Formulation --- p.27Chapter 2.2.3 --- Heterogeneous B*-Trees for Analog Placement with Symmetry and Regularity Considerations --- p.28Chapter 2.3 --- Summary --- p.31Chapter 3 --- Common-Centroid Analog Placement --- p.32Chapter 3.1 --- Problem Formulation --- p.33Chapter 3.2 --- Overview of Our Work --- p.35Chapter 3.3 --- Handling Common Centroid Constraints in Different Devices --- p.37Chapter 3.3.1 --- Common Centroid Placement of Resistors --- p.38Chapter 3.3.2 --- Common Centroid Placement of Transistors --- p.44Chapter 3.3.3 --- Common Centroid Placement of Capacitors --- p.47Chapter 3.4 --- Congestion Estimation and Layout Expansion --- p.50Chapter 3.4.1 --- Blockage-Aware Congestion Estimation --- p.51Chapter 3.4.2 --- Layout Expansion --- p.56Chapter 3.5 --- Simulated Annealing --- p.59Chapter 3.5.1 --- Types of Moves --- p.59Chapter 3.5.2 --- Handling Devices in Symmetry Group --- p.59Chapter 3.5.3 --- Cost Function of Simulated Annealing --- p.61Chapter 3.6 --- Summary --- p.62Chapter 4 --- Experimental Results and Monte-Carlo Simulations --- p.64Chapter 4.1 --- Study of Congestion-driven Layout Expansion --- p.64Chapter 4.2 --- Monte Carlo Simulations --- p.70Chapter 4.2.1 --- Devices Modeling --- p.70Chapter 4.2.2 --- Study of Layouts with and without Symmetry Groups --- p.71Chapter 4.2.3 --- Study of Layouts with and without Self-Symmetry Devices --- p.73Chapter 4.2.4 --- Study of Layouts with Different Number of Symmetry Groups --- p.74Chapter 4.2.5 --- Study of Large and Small Size Capacitors Array --- p.76Chapter 4.3 --- Comparison of Automatic and Manual Layouts using Monte Carlo Simulations --- p.79Chapter 5 --- Conclusion --- p.86Bibliography --- p.8

Analog layout design automation: ILP-based analog routers

The shrinking design window and high parasitic sensitivity in the advanced technology have imposed special challenges on the analog and radio frequency (RF) integrated circuit design. In this thesis, we propose a new methodology to address such a deficiency based on integer linear programming (ILP) but without compromising the capability of handling any special constraints for the analog routing problems. Distinct from the conventional methods, our algorithm utilizes adaptive resolutions for various routing regions. For a more congested region, a routing grid with higher resolution is employed, whereas a lower-resolution grid is adopted to a less crowded routing region. Moreover, we strengthen its speciality in handling interconnect width control so as to route the electrical nets based on analog constraints while considering proper interconnect width to address the acute interconnect parasitics, mismatch minimization, and electromigration effects simultaneously. In addition, to tackle the performance degradation due to layout dependent effects (LDEs) and take advantage of optical proximity correction (OPC) for resolution enhancement of subwavelength lithography, in this thesis we have also proposed an innovative LDE-aware analog layout migration scheme, which is equipped with our special routing methodology. The LDE constraints are first identified with aid of a special sensitivity analysis and then satisfied during the layout migration process. Afterwards the electrical nets are routed by an extended OPC-inclusive ILP-based analog router to improve the final layout image fidelity while the routability and analog constraints are respected in the meantime. The experimental results demonstrate the effectiveness and efficiency of our proposed methods in terms of both circuit performance and image quality compared to the previous works

Colloquium : disclination loops, point defects, and all that in nematic liquid crystals

The homotopy theory of topological defects is a powerful tool for organizing and unifying many ideas across a broad range of physical systems. Recently, experimental progress was made in controlling and measuring colloidal inclusions in liquid crystalline phases. The topological structure of these systems is quite rich but, at the same time, subtle. Motivated by experiment and the power of topological reasoning, the classification of defects in uniaxial nematic liquid crystals was reviewed and expounded upon. Particular attention was paid to the ambiguities that arise in these systems, which have no counterpart in the much-storied XY model or the Heisenberg ferromagnet

Physical Planning and Uncore Power Management for Multi-Core Processors

For the microprocessor technology of today and the foreseeable future, multi-core is a key engine that drives performance growth under very tight power dissipation constraints. While previous research has been mostly focused on individual processor cores, there is a compelling need for studying how to efficiently manage shared resources among cores, including physical space, on-chip communication and on-chip storage. In managing physical space, floorplanning is the first and most critical step that largely affects communication efficiency and cost-effectiveness of chip designs. We consider floorplanning with regularity constraints that requires identical processing/memory cores to form an array. Such regularity can greatly facilitate design modularity and therefore shorten design turn-around time. Very little attention has been paid to automatic floorplanning considering regularity constraints because manual floorplanning has difficulty handling the complexity as chip core count increases. In this dissertation work, we investigate the regularity constraints in a simulated-annealing based floorplanner for multi/many core processor designs. A simple and effective technique is proposed to encode the regularity constraints in sequence-pair, which is a classic format of data representation in automatic floorplanning. To the best of our knowledge, this is the first work on regularity-constrained floorplanning in the context of multi/many core processor designs. On-chip communication and shared last level cache (LLC) play a role that is at least as equally important as processor cores in terms of chip performance and power. This dissertation research studies dynamic voltage and frequency scaling for on-chip network and LLC, which forms a single uncore domain of voltage and frequency. This is in contrast to most previous works where the network and LLC are partitioned and associated with processor cores based on physical proximity. The single shared domain can largely avoid the interfacing overhead across domain boundaries and is practical and very useful for industrial products. Our goal is to minimize uncore energy dissipation with little, e.g., 5% or less, performance degradation. The first part of this study is to identify a metric that can reflect the chip performance determined by uncore voltage/frequency. The second part is about how to monitor this metric with low overhead and high fidelity. The last part is the control policy that decides uncore voltage/frequency based on monitoring results. Our approach is validated through full system simulations on public architecture benchmarks