Desenvolvimento de estruturas paralelas em FPGA e implementação de controladores digitais para aplicação em filtros ativos de potência

This paper presents a parallel approach to FPGA implementation of digital controllers, in order to reduce the computational time for implementing the control laws. The control technique used in the proposed implementation can be applied for selective harmonic compensation in active power filters (APF). To compensate for even a small number of harmonics requires multiple calculation instructions involving multiplications and additions. Thus, to improve the performance of the computer system is proposed to implement a parallel structure of the controller. To compensate for a larger number of harmonics is performed in the decomposition voltages of the harmonic components into their frames synchronous using the Discrete Fourier Transform. This strategy allows a calculation time fixed regardless of the number of harmonics up to the limit imposed by the sampling frequency. The experimental results are presented to compare the runtime of the proposed parallel approach with the sequential execution time conventionally used in the literature.Este trabalho apresenta uma abordagem paralela em FPGA para implementação de controladores digitais, com a finalidade de reduzir o tempo computacional de execução das leis de controle. A técnica de controle utilizada na implementação proposta pode ser aplicada para a compensação seletiva de harmônicos em filtros ativos de potência (FAP). Para compensar mesmo um número reduzido de harmônicas são necessárias múltiplas instruções de cálculo, envolvendo multiplicações e adições. Desta forma, para melhorar o desempenho computacional do sistema, é proposta uma estrutura paralela para implementação do controlador. Para compensação de um número maior de harmônicas é realizada a decomposição das tensões em suas componentes harmônicas em eixos síncronos utilizando a Transformada Discreta de Fourier. Esta estratégia permite um tempo de cálculo fixo independente do número de harmônicas, até o limite imposto pela frequência de amostragem. Os resultados experimentais são apresentados para comparar o tempo de execução da abordagem paralela proposta com o tempo de execução sequencial convencionalmente utilizado na literatura

Efficient implementation of video processing algorithms on FPGA

The work contained in this portfolio thesis was carried out as part of an Engineering Doctorate (Eng.D) programme from the Institute for System Level Integration. The work was sponsored by Thales Optronics, and focuses on issues surrounding the implementation of video processing algorithms on field programmable gate arrays (FPGA). A description is given of FPGA technology and the currently dominant methods of designing and verifying firmware. The problems of translating a description of behaviour into one of structure are discussed, and some of the latest methodologies for tackling this problem are introduced. A number of algorithms are then looked at, including methods of contrast enhancement, deconvolution, and image fusion. Algorithms are characterised according to the nature of their execution flow, and this is used as justification for some of the design choices that are made. An efficient method of performing large two-dimensional convolutions is also described. The portfolio also contains a discussion of an FPGA implementation of a PID control algorithm, an overview of FPGA dynamic reconfigurability, and the development of a demonstration platform for rapid deployment of video processing algorithms in FPGA hardware