Self-Reconfigurable Analog Arrays: Off-The Shelf Adaptive Electronics for Space Applications

Development of analog electronic solutions for space avionics is expensive and lengthy. Lack of flexible analog devices, counterparts to digital Field Programmable Gate Arrays (FPGA), prevents analog designers from benefits of rapid prototyping. This forces them to expensive and lengthy custom design, fabrication, and qualification of application specific integrated circuits (ASIC). The limitations come from two directions: commercial Field Programmable Analog Arrays (FPAA) have limited variability in the components offered on-chip; and they are only qualified for best case scenarios for military grade (-55C to +125C). In order to avoid huge overheads, there is a growing trend towards avoiding thermal and radiation protection by developing extreme environment electronics, which maintain correct operation while exposed to temperature extremes (-180degC to +125degC). This paper describes a recent FPAA design, the Self-Reconfigurable Analog Array (SRAA) developed at JPL. It overcomes both limitations, offering a variety of analog cells inside the array together with the possibility of self-correction at extreme temperatures

A Low-Power, Reconfigurable, Pipelined ADC with Automatic Adaptation for Implantable Bioimpedance Applications

Biomedical monitoring systems that observe various physiological parameters or electrochemical reactions typically cannot expect signals with fixed amplitude or frequency as signal properties can vary greatly even among similar biosignals. Furthermore, advancements in biomedical research have resulted in more elaborate biosignal monitoring schemes which allow the continuous acquisition of important patient information. Conventional ADCs with a fixed resolution and sampling rate are not able to adapt to signals with a wide range of variation. As a result, reconfigurable analog-to-digital converters (ADC) have become increasingly more attractive for implantable biosensor systems. These converters are able to change their operable resolution, sampling rate, or both in order convert changing signals with increased power efficiency. Traditionally, biomedical sensing applications were limited to low frequencies. Therefore, much of the research on ADCs for biomedical applications focused on minimizing power consumption with smaller bias currents resulting in low sampling rates. However, recently bioimpedance monitoring has become more popular because of its healthcare possibilities. Bioimpedance monitoring involves injecting an AC current into a biosample and measuring the corresponding voltage drop. The frequency of the injected current greatly affects the amplitude and phase of the voltage drop as biological tissue is comprised of resistive and capacitive elements. For this reason, a full spectrum of measurements from 100 Hz to 10-100 MHz is required to gain a full understanding of the impedance. For this type of implantable biomedical application, the typical low power, low sampling rate analog-to-digital converter is insufficient. A different optimization of power and performance must be achieved. Since SAR ADC power consumption scales heavily with sampling rate, the converters that sample fast enough to be attractive for bioimpedance monitoring do not have a figure-of-merit that is comparable to the slower converters. Therefore, an auto-adapting, reconfigurable pipelined analog-to-digital converter is proposed. The converter can operate with either 8 or 10 bits of resolution and with a sampling rate of 0.1 or 20 MS/s. Additionally, the resolution and sampling rate are automatically determined by the converter itself based on the input signal. This way, power efficiency is increased for input signals of varying frequency and amplitude

A Flexible RFIC Architecture for High-Sensitivity Reception and Compressed-Sampling Wideband Detection

Compressed sensing (CS) is a new signal processing approach that has disrupted the Shannon-Nyquist limit based design methodology and has opened promising avenues for building energy-efficient radio frequency integrated circuits (RFICs) for detecting and estimating particular classes (i.e. sparse) of signals. Whether in application domains where naturally occurring signals are sparse or where representations of signals subject to the fidelity limits or configuration settings of the radio equipment are often found to be sparse, the emergence of CS has forced us to re-imagine the radio receiver. While realizing some of the potential benefits promised by theory, CS-RFIC architectures proposed in earlier research were not particularly suitable for mass-market applications. This thesis demonstrates how to take a new signal processing technique all the way to the hardware level. So far, the main focus in literature has been how CS offers a significant advantage for signal processing. This work will show how CS techniques drive novel architectures down to the integrated circuit level. This requires close collaboration between communication system developers, integrated circuit designers and signal processing experts. The trans-disciplinary approach presented here has led to the unification of CS-inspired architectures for wideband signal detection with robust, legacy architectures for high-sensitivity signal reception. The result is a functionally flexible and rapidly reconfigurable CMOS RFIC compactly implemented on silicon with the potential to achieve the cost, size and power targets in mass-market applications. While the focus of this thesis is RF signal finding and reception in frequency, the CS-based RFIC design approach presented here is applicable to a wide range of other applications like direction-of-arrival and range finding. We begin by developing a signal-model driven approach for optimizing the performance of CS RF frontends (RFFEs). We consider sparse multiband signals with supports contained within a frequency span extending from fMIN to fMAX. The resulting quadrature analog-to-information converter (QAIC) is a flexible-bandwidth, blind sub-Nyquist sampling architecture optimized for energy consumption and sensitivity performance. The QAIC addresses key drawbacks of earlier CS RFFE architectures like the modulated wideband converter (MWC) that implement frequency spans extending from 0 to fMAX. While these earlier architectures, a direct implementation of CS signal processing theory, have several beneficial properties, the true cost of their proposed analog frontend significantly diminishes the sensitivity performance and energy savings that CS methods have the potential to deliver. They use periodic pseudo-random bit sequence (PRBS) generators where the clock frequency fPRBS scales up with the maximum signal frequency fMAX. In contrast, fPRBS in the QAIC RFFE scales up with the instantaneous bandwidth IBW, where IBW = ( fMAX − fMIN ). This results in significant performance advantages in terms of energy consumption and sensitivity performance. The QAIC uncouples fPRBS from fMAX by performing wideband quadrature downconversion ahead of analog mixing with PRBSs at an intermediate frequency (IF). However, the dual heterodyne architecture of the QAIC suffers from spurious responses at IF caused by gain and phase imbalance in its wideband downconverter. We then show how the direct RF-to-information converter (DRF2IC) compactly adds CS wideband detection to a direct conversion frequency-translational noise-cancelling (FTNC) receiver by introducing pseudo-random modulation of the local oscillator (LO) signals and by consolidating multiple CS measurements into one hardware branch. The DRF2IC inherits benefits of the FTNC receiver in signal reception mode. In CS wideband detection mode, the DRF2IC inherits key advantages from both the earlier lowpass CS architectures and the QAIC while avoiding the drawbacks of both. It uncouples fPRBS from fMAX in contrast with the MWC. In contrast with the QAIC, the DRF2IC employs a direct conversion RF chain with narrow bandwidth analog components at baseband thereby avoiding frequency-dependent gain and phase imbalance. The DRF2IC chip occupies 0.56mm2 area in 65nm CMOS. In reception mode, it consumes 46.5mW from 1.15V and delivers 40MHz RF bandwidth, 41.5dB conversion gain, 3.6dB noise figure (NF) and -2dBm blocker 1dB compression point (B1dB). In CS wideband detection mode, 66dB operational dynamic range, 40dB instantaneous dynamic range and 1.43GHz instantaneous bandwidth are demonstrated and 6 interferers each 10MHz wide scattered over a 1.27GHz span are detected in 1.2us consuming 58.5mW

1-D broadside-radiating leaky-wave antenna based on a numerically synthesized impedance surface

A newly-developed deterministic numerical technique for the automated design of metasurface antennas is applied here for the first time to the design of a 1-D printed Leaky-Wave Antenna (LWA) for broadside radiation. The surface impedance synthesis process does not require any a priori knowledge on the impedance pattern, and starts from a mask constraint on the desired far-field and practical bounds on the unit cell impedance values. The designed reactance surface for broadside radiation exhibits a non conventional patterning; this highlights the merit of using an automated design process for a design well known to be challenging for analytical methods. The antenna is physically implemented with an array of metal strips with varying gap widths and simulation results show very good agreement with the predicted performance

Beam scanning by liquid-crystal biasing in a modified SIW structure

A fixed-frequency beam-scanning 1D antenna based on Liquid Crystals (LCs) is designed for application in 2D scanning with lateral alignment. The 2D array environment imposes full decoupling of adjacent 1D antennas, which often conflicts with the LC requirement of DC biasing: the proposed design accommodates both. The LC medium is placed inside a Substrate Integrated Waveguide (SIW) modified to work as a Groove Gap Waveguide, with radiating slots etched on the upper broad wall, that radiates as a Leaky-Wave Antenna (LWA). This allows effective application of the DC bias voltage needed for tuning the LCs. At the same time, the RF field remains laterally confined, enabling the possibility to lay several antennas in parallel and achieve 2D beam scanning. The design is validated by simulation employing the actual properties of a commercial LC medium

An Investigation into Neuromorphic ICs using Memristor-CMOS Hybrid Circuits

The memristance of a memristor depends on the amount of charge flowing through it and when current stops flowing through it, it remembers the state. Thus, memristors are extremely suited for implementation of memory units. Memristors find great application in neuromorphic circuits as it is possible to couple memory and processing, compared to traditional Von-Neumann digital architectures where memory and processing are separate. Neural networks have a layered structure where information passes from one layer to another and each of these layers have the possibility of a high degree of parallelism. CMOS-Memristor based neural network accelerators provide a method of speeding up neural networks by making use of this parallelism and analog computation. In this project we have conducted an initial investigation into the current state of the art implementation of memristor based programming circuits. Various memristor programming circuits and basic neuromorphic circuits have been simulated. The next phase of our project revolved around designing basic building blocks which can be used to design neural networks. A memristor bridge based synaptic weighting block, a operational transconductor based summing block were initially designed. We then designed activation function blocks which are used to introduce controlled non-linearity. Blocks for a basic rectified linear unit and a novel implementation for tan-hyperbolic function have been proposed. An artificial neural network has been designed using these blocks to validate and test their performance. We have also used these fundamental blocks to design basic layers of Convolutional Neural Networks. Convolutional Neural Networks are heavily used in image processing applications. The core convolutional block has been designed and it has been used as an image processing kernel to test its performance.Comment: Bachelor's thesi

Design and development of a localization system for a sensor network in collective symbiotic organisms

The REPLICATOR project aims for developing self-adaptive and self-assembling organisms compounded of stand-alone robots. These robots can autonomously and dynamically dock with each other forming symbiotic structures. This system requires that each robot knows the position of the others. Therefore, this master thesis consists of the design, implementation and assessment of a low power and low cost localization system, based on the strength of the signal of the wireless communications protocol ZigBee. Furthermore, a dynamic ZigBee coordinator selection process was developed to separate the localization application and the system’s configuration. The proposed solution is a distributed, anchor-free, self-configuring, cooperative and concurrent algorithm. The localization is iteratively recalculated and updated using a Eucledian method. In order to reduce the errors produced by the fluctuations of the signal, a weighted approach, IIR and FIR filters; and a calibration process were implemented. It was found that the implemented localization system can achieve localization errors lower than five percent. However, these errors vary greatly depending upon several uncontrolled facts such as the environment in which the system is deployed and the radiation pattern of the antennas; and in addition, the errors increase exponentially with the distance

Intrinsic Hardware Evolution on the Transistor Level

This thesis presents a novel approach to the automated synthesis of analog circuits. Evolutionary algorithms are used in conjunction with a fitness evaluation on a dedicated ASIC that serves as the analog substrate for the newly bred candidate solutions. The advantage of evaluating the candidate circuits directly in hardware is twofold. First, it may speed up the evolutionary algorithms, because hardware tests can usually be performed faster than simulations. Second, the evolved circuits are guaranteed to work on a real piece of silicon. The proposed approach is realized as a hardware evolution system consisting of an IBM compatible general purpose computer that hosts the evolutionary algorithm, an FPGA-based mixed signal test board, and the analog substrate. The latter one is designed as a Field Programmable Transistor Array (FPTA) whose programmable transistor cells can be almost freely connected. The transistor cells can be configured to adopt one out of 75 different channel geometries. The chip was produced in a 0.6µm CMOS process and provides ample means for the input and output of analog signals. The configuration is stored in SRAM cells embedded in the programmable transistor cells. The hardware evolution system is used for numerous evolution experiments targeted at a wide variety of different circuit functionalities. These comprise logic gates, Gaussian function circuits, D/A converters, low- and highpass filters, tone discriminators, and comparators. The experimental results are thoroughly analyzed and discussed with respect to related work

Learning-based robotic manipulation for dynamic object handling : a thesis presented in partial fulfilment of the requirements for the degree of Doctor of Philosophy in Mechatronic Engineering at the School of Food and Advanced Technology, Massey University, Turitea Campus, Palmerston North, New Zealand

Figures are re-used in this thesis with permission of their respective publishers or under a Creative Commons licence.Recent trends have shown that the lifecycles and production volumes of modern products are shortening. Consequently, many manufacturers subject to frequent change prefer flexible and reconfigurable production systems. Such schemes are often achieved by means of manual assembly, as conventional automated systems are perceived as lacking flexibility. Production lines that incorporate human workers are particularly common within consumer electronics and small appliances. Artificial intelligence (AI) is a possible avenue to achieve smart robotic automation in this context. In this research it is argued that a robust, autonomous object handling process plays a crucial role in future manufacturing systems that incorporate robotics—key to further closing the gap between manual and fully automated production. Novel object grasping is a difficult task, confounded by many factors including object geometry, weight distribution, friction coefficients and deformation characteristics. Sensing and actuation accuracy can also significantly impact manipulation quality. Another challenge is understanding the relationship between these factors, a specific grasping strategy, the robotic arm and the employed end-effector. Manipulation has been a central research topic within robotics for many years. Some works focus on design, i.e. specifying a gripper-object interface such that the effects of imprecise gripper placement and other confounding control-related factors are mitigated. Many universal robotic gripper designs have been considered, including 3-fingered gripper designs, anthropomorphic grippers, granular jamming end-effectors and underactuated mechanisms. While such approaches have maintained some interest, contemporary works predominantly utilise machine learning in conjunction with imaging technologies and generic force-closure end-effectors. Neural networks that utilise supervised and unsupervised learning schemes with an RGB or RGB-D input make up the bulk of publications within this field. Though many solutions have been studied, automatically generating a robust grasp configuration for objects not known a priori, remains an open-ended problem. An element of this issue relates to a lack of objective performance metrics to quantify the effectiveness of a solution—which has traditionally driven the direction of community focus by highlighting gaps in the state-of-the-art. This research employs monocular vision and deep learning to generate—and select from—a set of hypothesis grasps. A significant portion of this research relates to the process by which a final grasp is selected. Grasp synthesis is achieved by sampling the workspace using convolutional neural networks trained to recognise prospective grasp areas. Each potential pose is evaluated by the proposed method in conjunction with other input modalities—such as load-cells and an alternate perspective. To overcome human bias and build upon traditional metrics, scores are established to objectively quantify the quality of an executed grasp trial. Learning frameworks that aim to maximise for these scores are employed in the selection process to improve performance. The proposed methodology and associated metrics are empirically evaluated. A physical prototype system was constructed, employing a Dobot Magician robotic manipulator, vision enclosure, imaging system, conveyor, sensing unit and control system. Over 4,000 trials were conducted utilising 100 objects. Experimentation showed that robotic manipulation quality could be improved by 10.3% when selecting to optimise for the proposed metrics—quantified by a metric related to translational error. Trials further demonstrated a grasp success rate of 99.3% for known objects and 98.9% for objects for which a priori information is unavailable. For unknown objects, this equated to an improvement of approximately 10% relative to other similar methodologies in literature. A 5.3% reduction in grasp rate was observed when removing the metrics as selection criteria for the prototype system. The system operated at approximately 1 Hz when contemporary hardware was employed. Experimentation demonstrated that selecting a grasp pose based on the proposed metrics improved grasp rates by up to 4.6% for known objects and 2.5% for unknown objects—compared to selecting for grasp rate alone. This project was sponsored by the Richard and Mary Earle Technology Trust, the Ken and Elizabeth Powell Bursary and the Massey University Foundation. Without the financial support provided by these entities, it would not have been possible to construct the physical robotic system used for testing and experimentation. This research adds to the field of robotic manipulation, contributing to topics on grasp-induced error analysis, post-grasp error minimisation, grasp synthesis framework design and general grasp synthesis. Three journal publications and one IEEE Xplore paper have been published as a result of this research