Desenvolvimento de um sistema em chip de processamento online para manutenção inteligente

Estratégias de monitoramento, baseadas na análise da condição de equipamentos utilizando ferramentas de processamento digital de sinais, inteligência artificial e tolerância a falhas, tornam-se cada vez mais necessárias nos processos industriais. As técnicas de manutenção inteligente conferem confiabilidade, disponibilidade e eficácia, e são estudadas, neste trabalho, no atual estado da arte. Porém, grande parte delas utiliza medidas com estados e parâmetros do processo que são dispendiosas e envolvem elevado tempo de amostragem e análise. O objetivo deste trabalho é desenvolver um novo sistema capaz de estimar a condição de saúde de um equipamento a partir das leituras de vibração e torque de sensores, e assim, viabilizar a detecção, predição e identificação de falhas online em atuadores elétricos utilizados em linhas de transporte de petróleo e/ou derivados. Para isso, foi desenvolvida uma técnica que, por meio de um dispositivo computacional, possibilita monitorar, considerando ruído e, de forma interativa, as variações dos parâmetros de um processo físico, tais como: falhas abruptas, incipientes e intermitentes. Isso corresponde às atividades de detecção, identificação de falhas e previsões sobre possíveis problemas que venham a surgir em consequência de pequenos desvios do comportamento normal do sistema. A metodologia empregada é baseada na estrutura do modelo Open Systems Architecture for Condition-Based Maintenance (OSA-CBM), que permite atuar nas seguintes camadas: 1) Aquisição de dados; 2) Manipulação de dados; 3) Monitoramento das condições; 4) Avaliação da saúde O sistema compreende a análise simultânea das propriedades de tempo e frequência do sinal, extração de características e filtragem adaptativa. Uma bancada de testes foi utilizada para reproduzir algumas falhas típicas que podem causar degradação na operação de atuadores fabricados no mercado. O sistema foi denominado Fault Detection System (FDS) e é baseado em técnicas de processamento de sinais que tem como saída um sinal de resíduo ou erro quando na ocorrência de uma falha correspondente nos equipamentos monitorados. A versão em software do sistema foi registrada no Instituto Nacional da Propriedade Industrial (INPI) no "BR 51 2016 000863-6". Uma nova versão para prototipagem em hardware do FDS em conjunto com um bloco auxiliar denominado Fault Detection Index (FDI), que também é proposto neste trabalho, foi desenvolvido na linguagem Verilog e implementado utilizando uma biblioteca Complementary Metal-Oxide-Semiconductor (CMOS) de 90 nm visando baixo consumo de energia ( 654 μW), baixa utilização de área em silício ( 0, 14 mm2) e processamento em tempo real. Os resultados demonstram a eficácia do método de detecção, diagnóstico e identificação de falhas apresentadas em atuadores elétricos empregados para controle de válvulas.Monitoring strategies based on the analysis of equipment condition with information derived from digital signal processing, artificial intelligence and fault tolerance tools become increasingly necessary in industrial process. In this context, intelligent maintenance techniques provide reliability, availability and are being increasingly studied in the current state of the art researches. However, most of them are based on measurements with states and process parameters that are costly and involve high sampling and analysis time. In order to avoid this problem, this work presents a new system capable of estimating the health condition of an equipment from the vibration and torque measurements of sensors, thus enabling online detection, prediction and identification of faults in electric actuators. The developed system represents a technique that, by means of a computational device, allows to monitor the variations of the parameters of a physical process such as abrupt, incipient and intermittent failures. This corresponds to the activities of fault detection, identification and prediction of possible problems that may arise due to minor deviations of the normal behavior state of the system. The methodology is based on the Open Systems Architecture for Condition-Based Maintenance (OSA-CBM) framework, which allows to act in the following layers: 1) Data acquisition; 2) Data manipulation; 3) Condition monitoring; 4) Health assessment. The system comprises the simultaneous analysis of signal time and frequency properties, feature extraction and adaptive filtering A testbench structure has been used to reproduce some typical faults that can cause degradation in the operation of the available commercial actuators. The results show the effectiveness of the method of detection, diagnosis and identification of faults that may occur in electric valves. The system is denominated Fault Detection System (FDS) and it is based on digital signal processing techniques producing a residue signal or error in the occurrence of a corresponding fault in the monitored equipment. A software version of the system was registered with the Instituto Nacional da Propriedade Industrial (INPI) no "BR 51 2016 000863-6". A new version for hardware prototyping of FDS together with the Fault Detection Index (FDI), which is also proposed in this work, was using Ver- ilog language and implemented in a 90 nm Complementary Metal-Oxide-Semiconductor (CMOS) library for low power consumption ( 654 μW), low silicon area utilization ( 0.14 mm2) and real time processing. The results demonstrate the effectiveness of the method of detection, diagnosis and identification of faults present in electric actuators used for controling fluidic valves

Efficient architectures for multidimensional discrete transforms in image and video processing applications

PhD ThesisThis thesis introduces new image compression algorithms, their related architectures and data transforms architectures. The proposed architectures consider the current hardware architectures concerns, such as power consumption, hardware usage, memory requirement, computation time and output accuracy. These concerns and problems are crucial in multidimensional image and video processing applications. This research is divided into three image and video processing related topics: low complexity non-transform-based image compression algorithms and their architectures, architectures for multidimensional Discrete Cosine Transform (DCT); and architectures for multidimensional Discrete Wavelet Transform (DWT). The proposed architectures are parameterised in terms of wordlength, pipelining and input data size. Taking such parameterisation into account, efficient non-transform based and low complexity image compression algorithms for better rate distortion performance are proposed. The proposed algorithms are based on the Adaptive Quantisation Coding (AQC) algorithm, and they achieve a controllable output bit rate and accuracy by considering the intensity variation of each image block. Their high speed, low hardware usage and low power consumption architectures are also introduced and implemented on Xilinx devices. Furthermore, efficient hardware architectures for multidimensional DCT based on the 1-D DCT Radix-2 and 3-D DCT Vector Radix (3-D DCT VR) fast algorithms have been proposed. These architectures attain fast and accurate 3-D DCT computation and provide high processing speed and power consumption reduction. In addition, this research also introduces two low hardware usage 3-D DCT VR architectures. Such architectures perform the computation of butterfly and post addition stages without using block memory for data transposition, which in turn reduces the hardware usage and improves the performance of the proposed architectures. Moreover, parallel and multiplierless lifting-based architectures for the 1-D, 2-D and 3-D Cohen-Daubechies-Feauveau 9/7 (CDF 9/7) DWT computation are also introduced. The presented architectures represent an efficient multiplierless and low memory requirement CDF 9/7 DWT computation scheme using the separable approach. Furthermore, the proposed architectures have been implemented and tested using Xilinx FPGA devices. The evaluation results have revealed that a speed of up to 315 MHz can be achieved in the proposed AQC-based architectures. Further, a speed of up to 330 MHz and low utilisation rate of 722 to 1235 can be achieved in the proposed 3-D DCT VR architectures. In addition, in the proposed 3-D DWT architecture, the computation time of 3-D DWT for data size of 144×176×8-pixel is less than 0.33 ms. Also, a power consumption of 102 mW at 50 MHz clock frequency using 256×256-pixel frame size is achieved. The accuracy tests for all architectures have revealed that a PSNR of infinite can be attained