76 research outputs found

    An Optimization Method for the Remanufacturing Dynamic Facility Layout Problem with Uncertainties

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    Remanufacturing is a practice of growing importance due to increasing environmental awareness and regulations. Facility layout design, as the cornerstone of effective facility planning, is concerned about resource localization for a well-coordinated workflow that leads to lower material handling costs and reduced lead times. However, due to stochastic returns of used products/components and their uncontrollable quality conditions, the remanufacturing process exhibits a high level of uncertainty challenging the facility layout design for remanufacturing. This paper undertakes this problem and presents an optimization method for remanufacturing dynamic facility layout with variable process capacities, unequal processing cells, and intercell material handling. A dynamic multirow layout model is presented for layout optimization and a modified simulated annealing heuristic is proposed toward the determination of optimal layout schemes. The approach is demonstrated through a machine tool remanufacturing system

    An Optimization Method for the Remanufacturing Dynamic Facility Layout Problem with Uncertainties

    Get PDF
    Remanufacturing is a practice of growing importance due to increasing environmental awareness and regulations. Facility layout design, as the cornerstone of effective facility planning, is concerned about resource localization for a well-coordinated workflow that leads to lower material handling costs and reduced lead times. However, due to stochastic returns of used products/components and their uncontrollable quality conditions, the remanufacturing process exhibits a high level of uncertainty challenging the facility layout design for remanufacturing. This paper undertakes this problem and presents an optimization method for remanufacturing dynamic facility layout with variable process capacities, unequal processing cells, and intercell material handling. A dynamic multirow layout model is presented for layout optimization and a modified simulated annealing heuristic is proposed toward the determination of optimal layout schemes. The approach is demonstrated through a machine tool remanufacturing system

    Mathematical optimization approaches for facility layout problems: The state-of-the-art and future research directions

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    Sem PDF conforme despacho. Fundacao para a Ciencia e a Tecnologia - PEstOE/MAT/UI0297/2014.Facility layout problems are an important class of operations research problems that has been studied for several decades. Most variants of facility layout are NP-hard, therefore global optimal solutions are difficult or impossible to compute in reasonable time. Mathematical optimization approaches that guarantee global optimality of solutions or tight bounds on the global optimal value have nevertheless been successfully applied to several variants of facility layout. This review covers three classes of layout problems, namely row layout, unequal-areas layout, and multifloor layout. We summarize the main contributions to the area made using mathematical optimization, mostly mixed integer linear optimization and conic optimization. For each class of problems, we also briefly discuss directions that remain open for future research.publishe

    PASQUAL: Parallel Techniques for Next Generation Genome Sequence Assembly

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    A factored sparse approximate inverse preconditioned conjugate gradient solver on graphics processing units

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    Graphics Processing Units (GPUs) exhibit significantly higher peak performance than conventional CPUs. However, in general only highly parallel algorithms can exploit their potential. In this scenario, the iterative solution to sparse linear systems of equations could be carried out quite efficiently on a GPU as it requires only matrix-by-vector products, dot products, and vector updates. However, to be really effective, any iterative solver needs to be properly preconditioned and this represents a major bottleneck for a successful GPU implementation. Due to its inherent parallelism, the factored sparse approximate inverse (FSAI) preconditioner represents an optimal candidate for the conjugate gradient-like solution of sparse linear systems. However, its GPU implementation requires a nontrivial recasting of multiple computational steps. We present our GPU version of the FSAI preconditioner along with a set of results that show how a noticeable speedup with respect to a highly tuned CPU counterpart is obtained

    The Single Row Routing Problem Revisited: A Solution Based on Genetic Algorithms

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    With the advent of VLSI technology, circuits with more than one million transistors have been integrated onto a single chip. As the complexity of ICs grows, the time and money spent on designing the circuits become more important. A large, often dominant, part of the cost and time required to design an IC is consumed in the routing operation. The routing of carriers, such as in IC chips and printed circuit boards, is a classical problem in Computer Aided Design. With the complexity inherent in VLSI circuits, high performance routers are necessary. In this paper, a crucial step in the channel routing technique, the single row routing (SRR) problem, is considered. First, we discuss the relevance of SRR in the context of the general routing problem. Secondly, we show that heuristic algorithms are far from solving the general problem. Next, we introduce evolutionary computation, and, in particular, genetic algorithms (GAs) as a justifiable method in solving the SRR problem. Finally, an efficient O(nk) complexity technique based on GAs heuristic is obtained to solve the general SRR problem containing n nodes. Experimental results show that the algorithm is faster and can often generate better results than many of the leading heuristics proposed in the literature

    Matching Multistage Schemes to Viscous Flow

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    Peer Reviewedhttp://deepblue.lib.umich.edu/bitstream/2027.42/76318/1/AIAA-2005-4708-327.pd

    Cost calculation for incremental hardware synthesis

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