Delay-insensitive ternary logic (DITL)

This thesis focuses on development of a Single Rail Ternary Voltage Delay-Insensitive paradigm called Delay-Insensitive Ternary Logic (DITL), which is based on NULL Convention Logic (NCL). Single rail asynchronous logic has potential advantages over Dual-Rail logic such as reduction of Power and Interconnect as well as Logic Area. The DITL concept is developed in steps of individual circuit components. These components are designed at the transistor level and are connected together to form a registered pipeline system. Some variations in pipeline design are also investigated --Abstract, page iii

Ternary logic to binary bit conversion using multiple input floating gate MOSFETS in 0.5 micron n-well CMOS technology

In the present work, a CMOS ternary to binary bit conversion technique has been proposed using multiple input floating gate MOSFETs. The proposed circuit has been implemented in 0.5 µm n-well CMOS technology. The ternary input signals of {-1, 0, +1} are represented as -3 V, 0 V and +3 V, respectively. The ternary input is given as a combination of any two of the three voltage levels and the 4-bit binary output is generated in which the left most bit is sign bit (SB) followed by most significant bit (MSB), second significant bit (SSB) and the least significant bit (LSB). The potential on the floating gate can be modified by either capacitive coupling with other conductors or by changing the stored charge on the floating gate. After each computation for a certain combination of inputs the floating gate carries a specific charge which has to be removed, or compensated for in order, to maintain integrity of the next computation. The four methods used commonly for modifying stored charge on the floating gate are UV radiation, tunneling, channel hot-electron injection and hopping through or trapping/de-trapping of charges. A simple method has been presented where the residual charge on the floating gate is by-passed and set to a certain biased initial value. Based on this initial value for the floating node voltage, the ratios of the values of the input capacitors which are capacitively coupled to the floating gate have been designed. The design was simulated in PSPICE and the output voltage at each stage of the converter was used to back calculate and model the ratios for the input capacitors as well as determine the biasing voltage on the floating gate