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Addressing On-Chip Power Conversion and Dissipation Issues in Many-Core System-on-a-Chip based on Conventional Silicon and Emerging Nanotechnologies
Title from PDF of title page viewed August 27, 2018Dissertation advisor: Masud H ChowdhuryVitaIncludes bibliographical references (pages 158-163)Thesis (Ph.D.)--School of Computing and Engineering and Department of Physics and Astronomy. University of Missouri--Kansas City, 2017Integrated circuits (ICs) are moving towards system-on-a-chip (SOC) designs. SOC
allows various small and large electronic systems to be implemented in a single chip. This
approach enables the miniaturization of design blocks that leads to high density transistor
integration, faster response time, and lower fabrication costs. To reap the benefits of SOC
and uphold the miniaturization of transistors, innovative power delivery and power
dissipation management schemes are paramount. This dissertation focuses on on-chip
integration of power delivery systems and managing power dissipation to increase the
lifetime of energy storage elements. We explore this problem from two different angels:
On-chip voltage regulators and power gating techniques. On-chip voltage regulators reduce
parasitic effects, and allow faster and efficient power delivery for microprocessors. Power
gating techniques, on the other hand, reduce the power loss incurred by circuit blocks
during standby mode.
Power dissipation (Ptotal = Pstatic and Pdynamic) in a complementary metal-oxide
semiconductor (CMOS) circuit comes from two sources: static and dynamic. A quadratic
dependency on the dynamic switching power and a more than linear dependency on static
power as a form of gate leakage (subthreshold current) exist. To reduce dynamic power
loss, the supply power should be reduced. A significant reduction in power dissipation
occurs when portions of a microprocessor operate at a lower voltage level. This reduction
in supply voltage is achieved via voltage regulators or converters. Voltage regulators are
used to provide a stable power supply to the microprocessor. The conventional off-chip
switching voltage regulator contains a passive floating inductor, which is difficult to be
implemented inside the chip due to excessive power dissipation and parasitic effects.
Additionally, the inductor takes a very large chip area while hampering the scaling process.
These limitations make passive inductor based on-chip regulator design very unattractive
for SOC integration and multi-/many-core environments. To circumvent the challenges,
three alternative techniques based on active circuit elements to replace the passive LC filter
of the buck convertor are developed. The first inductorless on-chip switching voltage
regulator architecture is based on a cascaded 2nd order multiple feedback (MFB) low-pass
filter (LPF). This design has the ability to modulate to multiple voltage settings via pulse
with modulation (PWM). The second approach is a supplementary design utilizing a hybrid
low drop-out scheme to lower the output ripple of the switching regulator over a wider
frequency range. The third design approach allows the integration of an entire power
management system within a single chipset by combining a highly efficient switching
regulator with an intermittently efficient linear regulator (area efficient), for robust and
highly efficient on-chip regulation.
The static power (Pstatic) or subthreshold leakage power (Pleak) increases with
technology scaling. To mitigate static power dissipation, power gating techniques are
implemented. Power gating is one of the popular methods to manage leakage power during
standby periods in low-power high-speed IC design. It works by using transistor based
switches to shut down part of the circuit block and put them in the idle mode. The efficiency
of a power gating scheme involves minimum Ioff and high Ion for the sleep transistor. A
conventional sleep transistor circuit design requires an additional header, footer, or both
switches to turn off the logic block. This additional transistor causes signal delay and
increases the chip area. We propose two innovative designs for next generation sleep
transistor designs. For an above threshold operation, we present a sleep transistor design
based on fully depleted silicon-on-insulator (FDSOI) device. For a subthreshold circuit
operation, we implement a sleep transistor utilizing the newly developed silicon-on
ferroelectric-insulator field effect transistor (SOFFET). In both of the designs, the ability
to control the threshold voltage via bias voltage at the back gate makes both devices more
flexible for sleep transistors design than a bulk MOSFET. The proposed approaches
simplify the design complexity, reduce the chip area, eliminate the voltage drop by sleep
transistor, and improve power dissipation. In addition, the design provides a dynamically
controlled Vt for times when the circuit needs to be in a sleep or switching mode.Introduction -- Background and literature review -- Fully integrated on-chip switching voltage regulator -- Hybrid LDO voltage regulator based on cascaded second order multiple feedback loop -- Single and dual output two-stage on-chip power management system -- Sleep transistor design using double-gate FDSOI -- Subthreshold region sleep transistor design -- Conclusio