3 research outputs found

    Multiprocessor-safe Wait-free Queue in RTSJ

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    Currently, most computer systems are running on multiprocessors (or multicores). Moreover, the number of cores inside the processor are expected to increase. To be able to utilise the increased computational power in these systems, developers are enforced to expose more parallelism within their applications. Multi-threading is one of the common techniques that are used to introduce parallelism within computer applications. Shared data structures are in the core of multi-threaded applications; these data structures facilitate the communication between the different threads to help in completing the designed tasks within the application. A control mechanism should be provided such that the access of any thread will not compromise the consistency and correctness of the data structure contents. The increased number of threads will result in an increased competition, this will lead to inevitable difficulties in understanding the interleaving scenarios at runtime, hence, the time analysis will be a very complex task. The Real-Time Specification for Java (RTSJ) introduces different shared queues that can facilitate communication between different threads within the application. However, these queues are uni-directional enabling communication between standard Java threads and the realtime thread classes, which the RTSJ introduces. The work presented in this thesis introduces a novel algorithm for concurrently accessing shared data structures in a shared memory multi-processor (or multi-core) systems. The proposed algorithm is implemented as an arraybased First-In-First-Out (FIFO) queue, which improves the scalability and time predictability in multi-threaded applications. The algorithm utilises the different features that the RTSJ introduces to ensure the time predictability

    An Almost Non-Blocking Stack

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    Non-blocking data structure implementations can be useful for performance and fault-tolerance reasons. And they are far easier to use correctly in a signal- or interrupt-handler context
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