Equalization of Third-Order Intermodulation Products in Wideband Direct Conversion Receivers

This paper reports a SAW-less direct-conversion receiver which utilizes a mixed-signal feedforward path to regenerate and adaptively cancel IM3 products, thus accomplishing system-level linearization. The receiver system performance is dominated by a custom integrated RF front end implemented in 130-nm CMOS and achieves an uncorrected out-of-band IIP3 of -7.1 dBm under the worst-case UMTS FDD Region 1 blocking specifications. Under IM3 equalization, the receiver achieves an effective IIP3 of +5.3 dBm and meets the UMTS BER sensitivity requirement with 3.7 dB of margin

Stereophonic acoustic echo cancellation employing selective-tap adaptive algorithms

Published versio

Frequency and fundamental signal measurement algorithms for distributed control and protection applications

Increasing penetration of distributed generation within electricity networks leads to the requirement for cheap, integrated, protection and control systems. To minimise cost, algorithms for the measurement of AC voltage and current waveforms can be implemented on a single microcontroller, which also carries out other protection and control tasks, including communication and data logging. This limits the frame rate of the major algorithms, although analogue to digital converters (ADCs) can be oversampled using peripheral control processors on suitable microcontrollers. Measurement algorithms also have to be tolerant of poor power quality, which may arise within grid-connected or islanded (e.g. emergency, battlefield or marine) power system scenarios. This study presents a 'Clarke-FLL hybrid' architecture, which combines a three-phase Clarke transformation measurement with a frequency-locked loop (FLL). This hybrid contains suitable algorithms for the measurement of frequency, amplitude and phase within dynamic three-phase AC power systems. The Clarke-FLL hybrid is shown to be robust and accurate, with harmonic content up to and above 28% total harmonic distortion (THD), and with the major algorithms executing at only 500 samples per second. This is achieved by careful optimisation and cascaded use of exact-time averaging techniques, which prove to be useful at all stages of the measurements: from DC bias removal through low-sample-rate Fourier analysis to sub-harmonic ripple removal. Platform-independent algorithms for three-phase nodal power flow analysis are benchmarked on three processors, including the Infineon TC1796 microcontroller, on which only 10% of the 2000 mus frame time is required, leaving the remainder free for other algorithms

Experimental Verification of a Harmonic-Rejection Mixing Concept using Blind Interference Canceling

Abstract—This paper presents the first practical experiments\ud on a harmonic rejection downconverter, which offers up to 75 dB of harmonic rejection, without an RF filter. The downconverter uses a two-stage approach; the first stage is an analog multipath/ multi-phase harmonic rejection mixer followed by a second stage providing additional harmonic rejection based on blind adaptive interference canceling in the discrete-time domain. The aim is to show its functional operation and to find practical performance limitations. Measurement results show that the harmonic rejection of the downconverter is insensitive to frontend nonlinearities and LO phase noise. The canceler cannot cope with DC offsets. The DC offsets are removed by highpass filters. The signal paths used to obtain an estimate of the interference must\ud be designed to provide as much attenuation of the desired signal as possible