Implementation of JPEG compression and motion estimation on FPGA hardware

A hardware implementation of JPEG allows for real-time compression in data intensivve applications, such as high speed scanning, medical imaging and satellite image transmission. Implementation options include dedicated DSP or media processors, FPGA boards, and ASICs. Factors that affect the choice of platform selection involve cost, speed, memory, size, power consumption, and case of reconfiguration. The proposed hardware solution is based on a Very high speed integrated circuit Hardware Description Language (VHDL) implememtation of the codec with prefered realization using an FPGA board due to speed, cost and flexibility factors; The VHDL language is commonly used to model hardware impletations from a top down perspective. The VHDL code may be simulated to correct mistakes and subsequently synthesized into hardware using a synthesis tool, such as the xilinx ise suite. The same VHDL code may be synthesized into a number of sifferent hardware architetcures based on constraints given. For example speed was the major constraint when synthesizing the pipeline of jpeg encoding and decoding, while chip area and power consumption were primary constraints when synthesizing the on-die memory because of large area. Thus, there is a trade off between area and speed in logic synthesis

Online Pattern Recognition for the ALICE High Level Trigger

The ALICE High Level Trigger has to process data online, in order to select interesting (sub)events, or to compress data efficiently by modeling techniques.Focusing on the main data source, the Time Projection Chamber (TPC), we present two pattern recognition methods under investigation: a sequential approach "cluster finder" and "track follower") and an iterative approach ("track candidate finder" and "cluster deconvoluter"). We show, that the former is suited for pp and low multiplicity PbPb collisions, whereas the latter might be applicable for high multiplicity PbPb collisions, if it turns out, that more than 8000 charged particles would have to be reconstructed inside the TPC. Based on the developed tracking schemes we show, that using modeling techniques a compression factor of around 10 might be achievableComment: Realtime Conference 2003, Montreal, Canada to be published in IEEE Transactions on Nuclear Science (TNS), 6 pages, 8 figure

Turbo Bayesian Compressed Sensing

Compressed sensing (CS) theory specifies a new signal acquisition approach, potentially allowing the acquisition of signals at a much lower data rate than the Nyquist sampling rate. In CS, the signal is not directly acquired but reconstructed from a few measurements. One of the key problems in CS is how to recover the original signal from measurements in the presence of noise. This dissertation addresses signal reconstruction problems in CS. First, a feedback structure and signal recovery algorithm, orthogonal pruning pursuit (OPP), is proposed to exploit the prior knowledge to reconstruct the signal in the noise-free situation. To handle the noise, a noise-aware signal reconstruction algorithm based on Bayesian Compressed Sensing (BCS) is developed. Moreover, a novel Turbo Bayesian Compressed Sensing (TBCS) algorithm is developed for joint signal reconstruction by exploiting both spatial and temporal redundancy. Then, the TBCS algorithm is applied to a UWB positioning system for achieving mm-accuracy with low sampling rate ADCs. Finally, hardware implementation of BCS signal reconstruction on FPGAs and GPUs is investigated. Implementation on GPUs and FPGAs of parallel Cholesky decomposition, which is a key component of BCS, is explored. Simulation results on software and hardware have demonstrated that OPP and TBCS outperform previous approaches, with UWB positioning accuracy improved by 12.8x. The accelerated computation helps enable real-time application of this work

Improved Random Demodulator for Compressed Sensing Applications

The advances in the field of signal processing have led to the continuous increase in the bandwidth of signals. Sampling these signals becomes harder and harder due to the increased bandwidth. This brings in need for a complex high rate ADCs to meet the Nyquist rate which is the minimum rate to avoid aliasing. For a given increase in bandwidth, there has to be a corresponding increase in the sampling rate of ADC. This might not be possible in the near future at the current rate of increase in bandwidth. Hence, there is a need to replace the current Nyquist rate sampling method by a process that relaxes the requirements but still keeps the quality of signal reconstruction good . Compressed sensing is a new technique in the field of signal acquisition. Compressed sensing allows a signal to be acquired below Nyquist rate if the signal is sparse in a given domain. Compressed sensing makes possible to acquire sparse signals at rates below Nyquist rate. Signals like audio and images are sparse and can be sampled at a rate below the Nyquist rate. The random demodulator (RD) is a hardware architecture that is used to implement compressed sensing. A direct implementation of compressed sensing in hardware requires several copies of the RD. To reduce the complexity fewer RDs can be used. Usage of fewer RDs comes at the cost of decreased signal reconstruction performance. The contribution of this thesis is about improving the efficiency of RD. First contribution of this thesis involves proposing a new RD architecture that improves signal reconstruction quality using a post-acquisition randomization step. The second contribution of this thesis is to develop a hardware platform for compressed sensing using field programmable analog arrays (FPAAs) and field programmable gate arrays (FPGAs). This platform can be used to test new architectures of RD in hardware