2 research outputs found
An Evaluation of Memory Sharing Performance for Heterogeneous Embedded SoCs with Many-Core Accelerators
Today’s systems-on-chip (SoCs) more and more conform to
the models envisioned by the Heterogeneous System Architecture
(HSA) foundation in which massively parallel, programmable
many-core accelerators (PMCAs) not only cooperate
but also coherently share memory with a powerful,
multi-core host processor. Allowing direct access to system
memory from both sides greatly simplifies application development,
but it increases the potential interference to the
memory system due to the PMCA.
In this work, we evaluate the impact of a PMCA’s memory
traffic on the host performance using the Xilinx Zynq-7000
SoC. This platform features a dual-core ARM Cortex-A9
CPU, as well as a field-programmable gate array (FPGA),
which we use to model a PMCA. Synthetic workload, real
benchmarks from the MiBench and ALPBench suites, and
collaborative workloads all show that the interference generated
by the PMCA can significantly reduce the memory
bandwidth seen by the host (on average up to 25% for host
applications)