3 research outputs found

    Study of effective calculation operation implementation remaining multi-bit numbers division on FPGA

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    The rapid enhanced in the fields of the computers that leads to rapid breaking for ciphering algorithms and for these reasons most of ciphering algorithm tried to used multidigit for ciphering texts or images. Using the multidigit will increase the safety of information and protected it from supercomputer from breaking the ciphering algorithms. The current information systems employ operations on finite fields of various structures (for example, cryptographic systems). In this instance, it's common to have to deal with enormous numbers (128 bits or more). The proposed operation of discovering the remainder of the division of multidigit numbers will considerably improve the speed of such systems if implemented

    Resource Optimal Truncated Multipliers for FPGAs

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    International audienceThis proposal presents the resource optimal design of truncated multipliers targeting field programmable gate arrays (FPGAs). In contrast to application specific integrated circuits (ASICs), the design for FPGAs has some distinct design challenges due to many possibilities of computing the partial products using logic-based or DSP-based sub-multipliers. To tackle this, we extend a previously proposed tiling methodology which translates the multiplier design into a geometrical problem: the target multiplier is represented by a board that has to be covered by tiles representing the sub-multipliers. The tiling with the least resources can be found with integer linear programming (ILP). Our extension considers the error of possibly unoccupied positions of the board and determines the tiling with the least resources that respects the maximal allowed error bound. This error bound is chosen such that a faithfully rounded truncated multiplier is obtained. Compared to previous designs that use a fixed number of guard bits or optimize at the level of the dot diagrams, this allows a much better use of sub-multipliers resulting in significant area savings without sacrificing the timing
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