Efficient Scheduling for SDMG CIOQ Switches

Combined input and output queuing (CIOQ) switches are being considered as high-performance switch architectures due to their ability to achieve 100% throughput and perfectly emulate output queuing (OQ) switch performance with a small speedup factor S. To realize a speedup factor S, a conventional CIOQ switch requires the switching fabric and memories to operate S times faster than the line rate. In this paper, we propose to use a CIOQ switch with space-division multiplexing expansion and grouped input/output ports (SDMG CIOQ switch for short) to realize speedup while only requiring the switching fabric and memories to operate at the line rate. The cell scheduling problem for the SDMG CIOQ switch is abstracted as a bipartite k-matching problem. Using fluid model techniques, we prove that any maximal size k-matching algorithm on an SDMG CIOQ switch with an expansion factor 2 can achieve 100% throughput assuming input line arrivals satisfy the strong law of large numbers (SLLN) and no input/output line is oversubscribed. We further propose an efficient and starvation-free maximal size k-matching scheduling algorithm, kFRR, for the SDMG CIOQ switch. Simulation results show that kFRR achieves 100% throughput for SDMG CIOQ switches with an expansion factor 2 under two SLLN traffic models, uniform traffic and polarized traffic, confirming our analysis

Proposal and performance analysis of a combined input and output queuing packet switch

Orientador: Shusaburo MotoyamaTese (doutorado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de ComputaçãoResumo: Neste trabalho é proposto um comutador de pacotes baseado em uma estrutura crossbar com m enlaces paralelos internos, denominado comutador CEP (Comutador Crossbar de Enlaces Paralelos), e com facilidade para prover qualidade de serviço (QoS ¿ Quality of Service). O comutador proposto utiliza uma combinação de filas na entrada e na saída. Os pacotes são transferidos dos buffers de entrada para os buffers de saída através de mxN linhas internas. Como as linhas internas e externas operam com a mesma velocidade, não há necessidade de aumentar a velocidade do clock interno, fazendo com que a estrutura proposta seja apropriada para comutadores de alta velocidade. O desempenho do comutador CEP é analisado admitindo pacotes de tamanho fixo (célula ATM) e pacotes de tamanho variável. O tempo médio de atraso dos pacotes e o tamanho médio das filas de entrada e de saída são avaliados por simulação e/ou por modelos analíticos, utilizando teoria de filasAbstract: A QoS (Quality of Service) provisioned CIOQ (Combined Input Output Queuing) switch using crossbar structure with m parallel lines per output port is proposed in this work. The packets at input buffers are transferred to the output buffers by means of mxN internal lines. Since all internal lines have the same speed as external links, no internal clock speedup is required so that the proposed structure is suited for high-speed switches. Switch models for analysis are proposed for both fixed and variable packet lengths and their performances, in terms of average packet waiting time and average queue size for both input and output buffers, are evaluated by simulation and/or analytically by means of queuing theory. The proposed switch also presents a feature that facilitates the choice of scheduler in order to satisfy the QoS of each class of serviceDoutoradoTelecomunicações e TelemáticaDoutor em Engenharia Elétric

A Qos Provisioned Cioq Packet Switch Using Crossbar Structure With M Internal Links

A QoS provisioned CIOQ switch using crossbar structure with m parallel lines per output port is proposed in this paper. The packets at input buffers are transferred to the output buffers by means of mxN internal lines. Since all internal lines have the same speed as external links, no internal clock speedup is required so that the proposed structure is suited for high-speed switches. The switch models for analysis are proposed and its performances are evaluated by means of queuing theory. The results show that only 2 internal links for each output port are sufficient for quick packet transfer from the input buffers to the output buffers. The proposed switch has also the feature that facilitates the choice of scheduler in order to satisfy the QoS of each class of service. © 2005 IEEE.2005241247Newman, P., Lyon, T., Minshall, G., Flow labeled IP: A connectionless approach to ATM (1996) Proc. IEEE Infocom '96, 3, pp. 1251-1260Rekhter, Y., Davie, B., Katz, D., Rosen, E., Swallow, G., Cisco systems' tag switching architecture overview (1997) IETF RFC, 2105. , FebruaryWiswanathan, A., Feldman, N., Boivie, R., Woundy, R., ARTS: Aggregate route-based IP switching (1997) IETF Internet Draft, , MarchNewman, P., Minshall, G., Lyon, T., Huston, L., IP switching and gigabit routers (1977) IEEE Comm. Magazine, pp. 64-69. , JanuaryMotoyama, S., Arantes, M.P., An IP switch with distributed scheduling (2002) IEE Electronics Letters, 38 (8), pp. 392-393. , AprilMinkenberg, C., Engbersen, T., A combined input and output queued packet-switched system based on PRIZMA switch-on-a-chip technology (2000) IEEE Commun. Magazine, 38 (12), pp. 70-77. , DecemberChuang, S.T., Goel, A., Nckeown, N., Prabhakar, B., Matching output queuing with a combined input output queued switch (1999) IEEE Journal on Selected Areas in Communications, 17 (6), pp. 1030-1039. , JuneYang, M., Zheng, S.Q., An efficient scheduling algorithm for CIOQ switches with space-division multiplexing expansion Proc. IEEE Infocom'2003Motoyama, S., Santos, C.R., A combined input-output queuing ATM switch with m internal links for cell transfer (2002) International Telecommunications Symposium, pp. 142-146. , SeptemberMotoyama, S., Santos, C.R., Performance analysis of a CIOQ ATM switch with m internal links for cell transfer (2002) 10th International Conference on Software, Telecommunications &ampComputer Networks - SoftCom 2002, pp. 636-640. , NovemberSantos, C.R., Motoyama, S., A QoS provisioned CIOQ ATM switch with m internal links (2004) 11th International Conference on Telecommunications - ICT 2004, pp. 698-703. , Fortaleza, Brazil, Augus