4,031 research outputs found
Bayesian Optimization Approach for Analog Circuit Synthesis Using Neural Network
Bayesian optimization with Gaussian process as surrogate model has been
successfully applied to analog circuit synthesis. In the traditional Gaussian
process regression model, the kernel functions are defined explicitly. The
computational complexity of training is O(N 3 ), and the computation complexity
of prediction is O(N 2 ), where N is the number of training data. Gaussian
process model can also be derived from a weight space view, where the original
data are mapped to feature space, and the kernel function is defined as the
inner product of nonlinear features. In this paper, we propose a Bayesian
optimization approach for analog circuit synthesis using neural network. We use
deep neural network to extract good feature representations, and then define
Gaussian process using the extracted features. Model averaging method is
applied to improve the quality of uncertainty prediction. Compared to Gaussian
process model with explicitly defined kernel functions, the
neural-network-based Gaussian process model can automatically learn a kernel
function from data, which makes it possible to provide more accurate
predictions and thus accelerate the follow-up optimization procedure. Also, the
neural-network-based model has O(N) training time and constant prediction time.
The efficiency of the proposed method has been verified by two real-world
analog circuits
A Review of Bayesian Methods in Electronic Design Automation
The utilization of Bayesian methods has been widely acknowledged as a viable
solution for tackling various challenges in electronic integrated circuit (IC)
design under stochastic process variation, including circuit performance
modeling, yield/failure rate estimation, and circuit optimization. As the
post-Moore era brings about new technologies (such as silicon photonics and
quantum circuits), many of the associated issues there are similar to those
encountered in electronic IC design and can be addressed using Bayesian
methods. Motivated by this observation, we present a comprehensive review of
Bayesian methods in electronic design automation (EDA). By doing so, we hope to
equip researchers and designers with the ability to apply Bayesian methods in
solving stochastic problems in electronic circuits and beyond.Comment: 24 pages, a draft version. We welcome comments and feedback, which
can be sent to [email protected]
Tensor Computation: A New Framework for High-Dimensional Problems in EDA
Many critical EDA problems suffer from the curse of dimensionality, i.e. the
very fast-scaling computational burden produced by large number of parameters
and/or unknown variables. This phenomenon may be caused by multiple spatial or
temporal factors (e.g. 3-D field solvers discretizations and multi-rate circuit
simulation), nonlinearity of devices and circuits, large number of design or
optimization parameters (e.g. full-chip routing/placement and circuit sizing),
or extensive process variations (e.g. variability/reliability analysis and
design for manufacturability). The computational challenges generated by such
high dimensional problems are generally hard to handle efficiently with
traditional EDA core algorithms that are based on matrix and vector
computation. This paper presents "tensor computation" as an alternative general
framework for the development of efficient EDA algorithms and tools. A tensor
is a high-dimensional generalization of a matrix and a vector, and is a natural
choice for both storing and solving efficiently high-dimensional EDA problems.
This paper gives a basic tutorial on tensors, demonstrates some recent examples
of EDA applications (e.g., nonlinear circuit modeling and high-dimensional
uncertainty quantification), and suggests further open EDA problems where the
use of tensor computation could be of advantage.Comment: 14 figures. Accepted by IEEE Trans. CAD of Integrated Circuits and
System
Post-Layout Simulation Driven Analog Circuit Sizing
Post-layout simulation provides accurate guidance for analog circuit design,
but post-layout performance is hard to be directly optimized at early design
stages. Prior work on analog circuit sizing often utilizes pre-layout
simulation results as the optimization objective. In this work, we propose a
post-layout-simulation-driven (post-simulation-driven for short) analog circuit
sizing framework that directly optimizes the post-layout simulation
performance. The framework integrates automated layout generation into the
optimization loop of transistor sizing and leverages a coupled Bayesian
optimization algorithm to search for the best post-simulation performance.
Experimental results demonstrate that our framework can achieve over 20% better
post-layout performance in competitive time than manual design and the method
that only considers pre-layout optimization
Practical Layout-Aware Analog/Mixed-Signal Design Automation with Bayesian Neural Networks
The high simulation cost has been a bottleneck of practical
analog/mixed-signal design automation. Many learning-based algorithms require
thousands of simulated data points, which is impractical for expensive to
simulate circuits. We propose a learning-based algorithm that can be trained
using a small amount of data and, therefore, scalable to tasks with expensive
simulations. Our efficient algorithm solves the post-layout performance
optimization problem where simulations are known to be expensive. Our
comprehensive study also solves the schematic-level sizing problem. For
efficient optimization, we utilize Bayesian Neural Networks as a regression
model to approximate circuit performance. For layout-aware optimization, we
handle the problem as a multi-fidelity optimization problem and improve
efficiency by exploiting the correlations from cheaper evaluations. We present
three test cases to demonstrate the efficiency of our algorithms. Our tests
prove that the proposed approach is more efficient than conventional baselines
and state-of-the-art algorithms.Comment: Accepted to the 42nd International Conference on Computer-Aided
Design (ICCAD 2023); 8 pages, 8 figure
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Versatile stochastic dot product circuits based on nonvolatile memories for high performance neurocomputing and neurooptimization.
The key operation in stochastic neural networks, which have become the state-of-the-art approach for solving problems in machine learning, information theory, and statistics, is a stochastic dot-product. While there have been many demonstrations of dot-product circuits and, separately, of stochastic neurons, the efficient hardware implementation combining both functionalities is still missing. Here we report compact, fast, energy-efficient, and scalable stochastic dot-product circuits based on either passively integrated metal-oxide memristors or embedded floating-gate memories. The circuit's high performance is due to mixed-signal implementation, while the efficient stochastic operation is achieved by utilizing circuit's noise, intrinsic and/or extrinsic to the memory cell array. The dynamic scaling of weights, enabled by analog memory devices, allows for efficient realization of different annealing approaches to improve functionality. The proposed approach is experimentally verified for two representative applications, namely by implementing neural network for solving a four-node graph-partitioning problem, and a Boltzmann machine with 10-input and 8-hidden neurons
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