4 research outputs found
OLT(RE)2: an On-Line on-demand Testing approach for permanent Radiation Effects in REconfigurable systems
Reconfigurable systems gained great interest in a wide range of application fields, including aerospace, where electronic devices are exposed to a very harsh working environment. Commercial SRAM-based FPGA devices represent an extremely interesting hardware platform for this kind of systems since they combine low cost with the possibility to utilize state-of-the-art processing power as well as the flexibility of reconfigurable hardware. In this paper we present OLT(RE)2: an on-line on-demand approach to test permanent faults induced by radiation in reconfigurable systems used in space missions. The proposed approach relies on a test circuit and on custom place-and-route algorithms. OLT(RE)2 exploits partial dynamic reconfigurability offered by today’s SRAM-based FPGAs to place the test circuits at run-time. The goal of OLT(RE)2 is to test unprogrammed areas of the FPGA before using them, thus preventing functional modules of the reconfigurable system to be placed on areas with faulty resources. Experimental results have shown that (i) it is possible to generate, place and route the test circuits needed to detect on average more than 99 % of the physical wires and on average about 97 % of the programmable interconnection points of an arbitrary large region of the FPGA in a reasonable time and that (ii) it is possible to download and run the whole test suite on the target device without interfering with the normal functioning of the system
Design and implementation of a routing algorithm to maximize test coverage of permanent faults in FPGAs
Nowadays electronic devices are used in a huge number of applications, from entertainment market to military equipment, from mobile phones to satellites. Each application has its own requirements and constraints depending on its purpose. One particular kind of applications is the one called mission critical that is characterized by a large amount of money that could be lost if something goes wrong. As an example this is the case of satellites that cannot be repaired or returned for maintenance if some parts stop working. When electronic device, and in particular FPGAs, are used in mission critical applications their reliability requires a special attention, therefore a key aspect of them is the capability to tolerate faults. When FPGAs operate in harsh environment, like in space, both temporary and permanent faults can occur due to radiation. The on-line testing technique involves a testing circuit that is capable to test its own used resources. In this work a design and implementation of a routing algorithm to maximize fault coverage of permanent faults is presented
Characterisation and mitigation of long-term degradation effects in programmable logic
Reliability has always been an issue in silicon device engineering, but until now it has been
managed by the carefully tuned fabrication process. In the future the underlying physical
limitations of silicon-based electronics, plus the practical challenges of manufacturing with such
complexity at such a small scale, will lead to a crunch point where transistor-level reliability must
be forfeited to continue achieving better productivity.
Field-programmable gate arrays (FPGAs) are built on state-of-the-art silicon processes, but it
has been recognised for some time that their distinctive characteristics put them in a favourable
position over application-specific integrated circuits in the face of the reliability challenge. The
literature shows how a regular structure, interchangeable resources and an ability to reconfigure
can all be exploited to detect, locate, and overcome degradation and keep an FPGA application
running.
To fully exploit these characteristics, a better understanding is needed of the behavioural
changes that are seen in the resources that make up an FPGA under ageing. Modelling is an
attractive approach to this and in this thesis the causes and effects are explored of three important
degradation mechanisms. All are shown to have an adverse affect on FPGA operation, but their
characteristics show novel opportunities for ageing mitigation.
Any modelling exercise is built on assumptions and so an empirical method is developed
for investigating ageing on hardware with an accelerated-life test. Here, experiments show that
timing degradation due to negative-bias temperature instability is the dominant process in the
technology considered.
Building on simulated and experimental results, this work also demonstrates a variety of methods for increasing the lifetime of FPGA lookup tables. The pre-emptive measure of wear-levelling
is investigated in particular detail, and it is shown by experiment how di fferent reconfiguration
algorithms can result in a significant reduction to the rate of degradation