3 research outputs found
A Flip-Flop Matching Engine to Verify Sequential Optimizations
Equivalence checking tools often use a flip-flop matching step to avoid the state space traversal. Due to sequential optimizations performed during synthesis (merge, replication, redundancy removal, ...) and don't care conditions, the matching step can be very complex as well as incomplete. If the matching is incomplete, even the use of a fast and efficient SAT solver during the combinational equivalence-checking step may not prevent the failure of this approach. In this paper, we present a flip-flop matching engine, which is able to verify optimized circuits and handle don't care conditions
Record and play: a structural fixed point iteration for sequential circuit verification
Abstract This paper propose
Record and play: a structural fixed point iteration for sequential circuit verification
Abstract This paper propose