Satisfiability Modulo Theory based Methodology for Floorplanning in VLSI Circuits

This paper proposes a Satisfiability Modulo Theory based formulation for floorplanning in VLSI circuits. The proposed approach allows a number of fixed blocks to be placed within a layout region without overlapping and at the same time minimizing the area of the layout region. The proposed approach is extended to allow a number of fixed blocks with ability to rotate and flexible blocks (with variable width and height) to be placed within a layout without overlap. Our target in all cases is reduction in area occupied on a chip which is of vital importance in obtaining a good circuit design. Satisfiability Modulo Theory combines the problem of Boolean satisfiability with domains such as convex optimization. Satisfiability Modulo Theory provides a richer modeling language than is possible with pure Boolean SAT formulas. We have conducted our experiments on MCNC and GSRC benchmark circuits to calculate the total area occupied, amount of deadspace and the total CPU time consumed while placing the blocks without overlapping. The results obtained shows clearly that the amount of dead space or wasted space is reduced if rotation is applied to the blocks.Comment: 8 pages,5 figure

The generalized 3-connectivity of Cartesian product graphs

The generalized connectivity of a graph, which was introduced recently by Chartrand et al., is a generalization of the concept of vertex connectivity. Let $S$ be a nonempty set of vertices of $G$, a collection $\{T_1,T_2,...,T_r\}$ of trees in $G$ is said to be internally disjoint trees connecting $S$ if $E(T_i)\cap E(T_j)=\emptyset$ and $V(T_i)\cap V(T_j)=S$ for any pair of distinct integers $i,j$, where $1\leq i,j\leq r$. For an integer $k$ with $2\leq k\leq n$, the $k$-connectivity $\kappa_k(G)$ of $G$ is the greatest positive integer $r$ for which $G$ contains at least $r$ internally disjoint trees connecting $S$ for any set $S$ of $k$ vertices of $G$. Obviously, $\kappa_2(G)=\kappa(G)$ is the connectivity of $G$. Sabidussi showed that $\kappa(G\Box H) \geq \kappa(G)+\kappa(H)$ for any two connected graphs $G$ and $H$. In this paper, we first study the 3-connectivity of the Cartesian product of a graph $G$ and a tree $T$, and show that $(i)$ if $\kappa_3(G)=\kappa(G)\geq 1$, then $\kappa_3(G\Box T)\geq \kappa_3(G)$; $(ii)$ if $1\leq \kappa_3(G)< \kappa(G)$, then $\kappa_3(G\Box T)\geq \kappa_3(G)+1$. Furthermore, for any two connected graphs $G$ and $H$ with $\kappa_3(G)\geq\kappa_3(H)$, if $\kappa(G)>\kappa_3(G)$, then $\kappa_3(G\Box H)\geq \kappa_3(G)+\kappa_3(H)$; if $\kappa(G)=\kappa_3(G)$, then $\kappa_3(G\Box H)\geq \kappa_3(G)+\kappa_3(H)-1$. Our result could be seen as a generalization of Sabidussi's result. Moreover, all the bounds are sharp.Comment: 17 page

Design of Digital Parity Generator Layout Using 0.7 micron Technology

The proposed digital parity generator circuit is an integrated circuit functions to detect data errors at the transmitter end, and check it at the receiving end. In digital communications, the digital messages are transmitted in the form of 1’s and 0’s between two points. It is an error free if both are the same. The purpose of this research is to implement a design method of digital parity generator layout with 0.7 micron process technology ECPD07 from Tanner Tools. Layout design starts from making schematic circuit, test function and make a layout. Next, check the layout results in terms of design rules and verify the desired functionality gradually. The results show that the circuit has functioned well as an odd parity generator. The simulation results obtained with loads CL = 25 fF, tpLH = 2nS and tpHL = 1.46 nS indicate that tp = 1.73nS or operating frequency of 578 MHz. The integrated digital parity generator circuit using transmission gate has a size of 14758 um2 (78.5 um x188 um), consisting of 74 gates