Effects of varying laser trimming geometries on thin film resistors

Purpose - This paper studies the effects of varying laser trim patterns on several performance parameters of thin film resistors such as the temperature coefficient of resistance (TCR) and target resistance value. Design/methodology/approach - The benefits and limitations of basic trim patterns are taken into consideration and the plunge cut, double plunge cut and the curved L-cut were selected to be modelled and tested experimentally. A computer simulation of the laser trim patterns has been developed for the modelling process of the resistors. The influence of the trim length and resistor dimensions on the TCR performance and resistance value of the resistors is investigated. Findings - It is found that variation in trim length, within the range of 5 to 15 mm, can give significant increases in the TCR of the thin films. Thus, for the plunge TCR cut can reach up to 11.51 ppm/oC, for the double plunge cut up to 14.34 ppm/oC and for the curved L-cut up to 5.11 ppm/oC. Originality/value – Research on the effects of various laser trimming geometries on the TCR and target resistance accuracy is limited, especially for patterns such as the curved L-cut,which is investigated in this paper

Caractérisation électrique et vieillissement de résistances de silicium polycristallin modifiées par laser

La technologie CMOS et les procédés de fabrication conventionnels pour des circuits intégrés sont associés à une incertitude sur la valeur des composants. Cette variabilité des procédés de fabrication peut avoir des conséquences sur les performances des circuits et plus particulièrement dans le domaine des circuits analogiques. De nos jours, les circuits intégrés sont constitués de technologies numériques qui tolèrent une incertitude de fabrication et de composants analogiques, tels que des résistances, qui nécessitent un ajustement précis de leur valeur. Cet ajustement peut être effectué à l’aide d’une méthode de post-fabrication ou bien par une modification du procédé de fabrication, afin d’obtenir des circuits performants et compétitifs. Plusieurs méthodes ont été développées pour améliorer les performances des résistances par des méthodes de post-fabrication dont l’ajustement de la valeur des résistances par laser. Dans ce mémoire, les composants utilisés sont des résistances de silicium polycristallin (Poly-Si) fabriquées à l’aide d’une technologie CMOS de 180 nm sur des circuits intégrés permettant une intervention laser sur la surface des résistances. Pour réaliser les différents ajustements, un laser pulsé nanoseconde est utilisé dont la fluence d’opération est située autour ou en dessous de la fluence seuil de fonte du Poly-Si pour éviter des dommages à la structure du matériau. Cette méthode présente plusieurs avantages dont la diminution des risques d’endommager des circuits sensibles environnants. En effet, la forte localisation du traitement par laser permet de ne pas affecter les autres composants du circuit lors d’une intervention. De plus, les structures utilisées ne nécessitent pas d’étapes de fabrication supplémentaires, ce qui permet de réduire les coûts et prend peu de place sur le circuit. Cette méthode permet de réaliser un ajustement fin, précis et reproductible de la résistance avec une erreur maximale de 500 ppm. L’objectif de ce projet de maîtrise est d’analyser les différents paramètres laser qui permettent d’obtenir un ajustement précis des résistances avec la meilleure stabilité possible. Des mesures par spectroscopie Raman permettent d’observer et de caractériser les changements structuraux sur la couche de Poly-Si engendrés par l’intervention laser. Les mesures électriques de plusieurs résistances permettent de caractériser les paramètres laser permettant d’obtenir les composants les plus performants et les plus stables lors d’une irradiation par laser. Des mesures ont été réalisées à l’aide d’un four de chauffage pour simuler le vieillissement prématuré des structures et pour pouvoir caractériser la stabilité des résistances dans le temps. Il est démontré----------Abstract Several classes of integrated microelectronic circuits require highly precise and stable analog components that cannot be obtained directly through standard CMOS fabrication processes. Those components must thus be calibrated either by a modification of the fabrication process or by the application of a post-fabrication tuning procedure. Many successful post-fabrication tuning processes have been introduced in the field of resistor calibration, including resistor laser trimming which is the core subject of this thesis. In this thesis, trimmed components are standard CMOS 180nm technology polysilicon resistors, integrated in circuits specially designed to allow laser intervention on their surface. The laser used is a nanosecond pulsed laser for which the fluence is set below the melting threshold of polysilicon in order to prevent damage to the material structure. This novel low-power highly localized procedure reduces the risk of damaging sensitive surrounding circuits and requires no additional fabrication step, allowing smaller dies areas and reduced costs. Precise, reliable and reproducible devices have been tuned using this technique with a precision below 500 ppm. The main objective of this research is to study and analyze the effect of the laser parameters variation on the trimmed component properties and to optimize those parameters in regard of the desired precision and stability of the final product. Raman spectroscopic measurements are performed to observe and characterize structural modifications of the polysilicon material following laser irradiation as precise resistance measurements and standardized in-oven aging tests allow the complete characterization of the device in regard of precision and stability. It is shown that for a given precision, this novel low-power trimming technique produces devices with a stability comparable to those obtained with another trimming technology such as the pulsed current method. An electrical model is also developed to predict the resistance modification with the laser fluence, the number of pulses as well as the duration of those pulses. The model is shown to be 1 500 ppm accurate when laser fluence is set accordingly to the melting threshold of polysilicon. Concerning stability, results show that, following a 300 h, 150 °C aging procedure, laser trimmed components present a 1.2% resistance drift from their initial resistance value whereas a 0.7% drift is observed on untrimmed samples. Those results are comparable to those obtained with the pulsed current trimming technique which produces trimmed component with a 1% resistance drift following a 200 h 162 °C aging procedure

Low-frequency noise in downscaled silicon transistors: Trends, theory and practice

By the continuing downscaling of sub-micron transistors in the range of few to one deca-nanometers, we focus on the increasing relative level of the low-frequency noise in these devices. Large amount of published data and models are reviewed and summarized, in order to capture the state-of-the-art, and to observe that the 1/area scaling of low-frequency noise holds even for carbon nanotube devices, but the noise becomes too large in order to have fully deterministic devices with area less than 10nm×10nm. The low-frequency noise models are discussed from the point of view that the noise can be both intrinsic and coupled to the charge transport in the devices, which provided a coherent picture, and more interestingly, showed that the models converge each to other, despite the many issues that one can find for the physical origin of each model. Several derivations are made to explain crossovers in noise spectra, variable random telegraph amplitudes, duality between energy and distance of charge traps, behaviors and trends for figures of merit by device downscaling, practical constraints for micropower amplifiers and dependence of phase noise on the harmonics in the oscillation signal, uncertainty and techniques of averaging by noise characterization. We have also shown how the unavoidable statistical variations by fabrication is embedded in the devices as a spatial “frozen noise”, which also follows 1/area scaling law and limits the production yield, from one side, and from other side, the “frozen noise” contributes generically to temporal 1/f noise by randomly probing the embedded variations during device operation, owing to the purely statistical accumulation of variance that follows from cause-consequence principle, and irrespectively of the actual physical process. The accumulation of variance is known as statistics of “innovation variance”, which explains the nearly log-normal distributions in the values for low-frequency noise parameters gathered from different devices, bias and other conditions, thus, the origin of geometric averaging in low-frequency noise characterizations. At present, the many models generally coincide each with other, and what makes the difference, are the values, which, however, scatter prominently in nanodevices. Perhaps, one should make some changes in the approach to the low-frequency noise in electronic devices, to emphasize the “statistics behind the numbers”, because the general physical assumptions in each model always fail at some point by the device downscaling, but irrespectively of that, the statistics works, since the low-frequency noise scales consistently with the 1/area law