Addressing Queuing Bottlenecks at High Speeds

Modern routers and switch fabrics can have hundreds of input and output ports running at up to 10 Gb/s; 40 Gb/s systems are starting to appear. At these rates, the performance of the buffering and queuing subsystem becomes a significant bottleneck. In high performance routers with more than a few queues, packet buffering is typically implemented using DRAM for data storage and a combination of off-chip and on-chip SRAM for storing the linked-list nodes and packet length, and the queue headers, respectively. This paper focuses on the performance bottlenecks associated with the use of off-chip SRAM. We show how the combination of implicit buffer pointers and multi-buffer list nodes can dramatically reduce the impact of buffering and queuing subsystem on queuing performance. We also show how combining it with coarse-grained scheduling can improve the performance of fair queuing algorithms, while also reducing the amount of off-chip memory and bandwidth needed. These techniques can reduce the amount of SRAM needed to hold the list nodes by a factor of 10 at the cost of about 10% wastage of the DRAM space, assuming an aggregation degree of 16

Passenger Flows in Underground Railway Stations and Platforms, MTI Report 12-43

Urban rail systems are designed to carry large volumes of people into and out of major activity centers. As a result, the stations at these major activity centers are often crowded with boarding and alighting passengers, resulting in passenger inconvenience, delays, and at times danger. This study examines the planning and analysis of station passenger queuing and flows to offer rail transit station designers and transit system operators guidance on how to best accommodate and manage their rail passengers. The objectives of the study are to: 1) Understand the particular infrastructural, operational, behavioral, and spatial factors that affect and may constrain passenger queuing and flows in different types of rail transit stations; 2) Identify, compare, and evaluate practices for efficient, expedient, and safe passenger flows in different types of station environments and during typical (rush hour) and atypical (evacuations, station maintenance/ refurbishment) situations; and 3) Compile short-, medium-, and long-term recommendations for optimizing passenger flows in different station environments

Performance Implications of NoCs on 3D-Stacked Memories: Insights from the Hybrid Memory Cube

Memories that exploit three-dimensional (3D)-stacking technology, which integrate memory and logic dies in a single stack, are becoming popular. These memories, such as Hybrid Memory Cube (HMC), utilize a network-on-chip (NoC) design for connecting their internal structural organizations. This novel usage of NoC, in addition to aiding processing-in-memory capabilities, enables numerous benefits such as high bandwidth and memory-level parallelism. However, the implications of NoCs on the characteristics of 3D-stacked memories in terms of memory access latency and bandwidth have not been fully explored. This paper addresses this knowledge gap by (i) characterizing an HMC prototype on the AC-510 accelerator board and revealing its access latency behaviors, and (ii) by investigating the implications of such behaviors on system and software designs

Evaluation of Road Traffic Congestion by Shock Wave Theory and Reduction Strategies

Road traffic congestion continues to remain a major problem in most cities around the world, especially in developing countries resulting in extensive delays, improved fuel wastage and financial losses. Urban traffic congestion has been a difficult problem in the growth of modern cities in India. The factors that reason the traffic congestion are complex and they mutually restrict. Transportation researchers have long struggled to find adequate ways of describing and analysing traffic congestion, as marked from the large number of often challenging approaches and models that have been developed. In this study, we explain traffic flow model with shockwave theory and operational strategies to manage traffic congestion in developing countries like India. Monitoring traffic density and speed helps to better manage traffic flow and plan transport infrastructure and policy. In this study, we present techniques to measure traffic density and speed in unplanned traffic, common in developing countries, and apply those techniques to better understand traffic patterns

Revisiting the empirical fundamental relationship of traffic flow for highways using a causal econometric approach

The fundamental relationship of traffic flow is empirically estimated by fitting a regression curve to a cloud of observations of traffic variables. Such estimates, however, may suffer from the confounding/endogeneity bias due to omitted variables such as driving behaviour and weather. To this end, this paper adopts a causal approach to obtain an unbiased estimate of the fundamental flow-density relationship using traffic detector data. In particular, we apply a Bayesian non-parametric spline-based regression approach with instrumental variables to adjust for the aforementioned confounding bias. The proposed approach is benchmarked against standard curve-fitting methods in estimating the flow-density relationship for three highway bottlenecks in the United States. Our empirical results suggest that the saturated (or hypercongested) regime of the estimated flow-density relationship using correlational curve fitting methods may be severely biased, which in turn leads to biased estimates of important traffic control inputs such as capacity and capacity-drop. We emphasise that our causal approach is based on the physical laws of vehicle movement in a traffic stream as opposed to a demand-supply framework adopted in the economics literature. By doing so, we also aim to conciliate the engineering and economics approaches to this empirical problem. Our results, thus, have important implications both for traffic engineers and transport economists