A Study on Buffer Distribution for RRAM-based FPGA Routing Structures

Compared to Application-Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs) provide reconfigurablity at the cost of lower performance and higher power consumption. Exploiting a large number of programmable switches, routing structures are mainly responsible for the performance limitation. Hence, employing more efficient switches can drastically improve the performance and reduce the power consumption of the FPGA. Resistive Random Access Memory (RRAM)-based switches are one of the most promising candidates to improve the FPGA routing architecture thanks to their low on-resistance and non-volatility. The lower RC delay of RRAM-based routing multiplexers, as compared to CMOS-based routing structures encourages us to reconsider the buffer distribution in FPGAs. This paper proposes an approach to reduce the number of buffers in the routing path of RRAM-based FPGAs. Our architectural simulations show that the use of RRAM switches improves the critical path delay by 56% as compared to CMOS switches in standard FPGA circuits at 45-nm technology node while, at the same time, the area and power are reduced, respectively, by 17% and 9%. By adapting the buffering scheme, an extra bonus of 9% for delay reduction, 5% for power reduction and 16% for area reduction can be obtained, as compared to the conventional buffering approach for RRAM-based FPGAs

TCP-Mobile Edge: Accelerating Delivery in Mobile Networks

Abstract-Owing to the imminent fixed mobile convergence, Internet applications are frequently accessed through mobile nodes. However, service delivery latency is too high to satisfy user expectations. In this paper, we design a new TCP algorithm, TCP-ME (Mobile Edge), to accelerate the service delivery in mobile networks. Considering the QoS (Quality of Service) mechanisms of mobile networks, TCP-ME is designed to differentiate the packet loss caused by wireless errors, traffic conditioning of mobile core networks, and Internet congestion, as well as to react to the packet loss accordingly. To detect wireless errors, we mark the ACK (Acknowledge) packets in the uplink direction at the base station, and the marking threshold is a function of the instantaneous downlink queue length and the number of consecutive HARQ retransmissions. We modify the ECN mechanism with deterministic marking to detect Internet congestion. The packet loss caused by traffic conditioners of mobile networks is detected by whether the incoming DUPACK is marked or not. TCP-ME adapts the inter-packet interval when the packet loss is caused by wireless errors or the admission control mechanism. If the packet loss is due to Internet congestion, TCP-ME applies the TCP-New Reno's congestion window adaptation algorithm. Simulation results show that TCP-ME can speed up web service response time in mobile networks by about 80%

Joint hop-by-hop and receiver-driven interest control protocol for content-centric networks

Content-centric networking (CCN) advocates a new trans-port model tailored to named-data communication. Three features distinguish CCN transport from the TCP/IP model: unique endpoint at the receiver, pull-based data retrieval in a point to multi-point fashion and in-path caching. The definition of transport control mechanisms is of fun-damental importance within the CCN architectural design and beyond, in the broader scope of information-centric net-works. In this work, we propose a joint Hop-by-hop and Receiver-driven Interest Control Protocol (HR-ICP) to reg-ulate user requests (Interests) either at the receiver and at intermediate nodes via Interest shaping. We prove that HR-ICP is stable and converges to an efficient and max-min fair equilibrium. Compared to controlling traffic only at the re-ceiver, HR-ICP accelerates congestion reaction and reduces the loss rate, as we show by means of CCN packet-level sim-ulations. In different network scenarios, we highlight the advantages of our solution in terms of faster convergence to the optimal throughput, robustness against misbehaving re-ceivers and flow protection of delay-sensitive applications

Flow Control at Satellite Gateways

Abstract-- Broadcast satellite networks are going play an important role in the global information infrastructure. Several systems including DirecWayfrom Hughes Network System use satellites to provide direct-to-user high speed Internet services. TCP works well in the terrestrial fiber networks but does not work well in satellite hybrid (satellite-terrestrial) networks. In this paper we analyze the problems that cause this dramatically degradedperformance. Based on the observation that it difficult for an end-to-end solution to solve these problems in this kind of hybrid networks, we propose a connection splitting based solution. A rate-based protocol is designed for the satellite connections and a flow control scheme at the satellite gateways (SGW) used to couple the two split connections together.Our simulation results shows that our scheme can maintain high utilization of the satellite link and improve fairness among the competing connections

Design and stability analysis of high performance packet switches

With the rapid development of optical interconnection technology, high-performance packet switches are required to resolve contentions in a fast manner to satisfy the demand for high throughput and high speed rates. Combined input-crosspoint buffered (CICB) switches are an alternative to input-buffered (IB) packet switches to provide high-performance switching and to relax arbitration timing for packet switches with high-speed ports. A maximum weight matching (MWM) scheme can provide 100% throughput under admissible traffic for lB switches. However, the high complexity of MWM prohibits its implementation in high-speed switches. In this dissertation, a feedback-based arbitration scheme for CICB switches is studied, where cell selection is based on the provided service to virtual output queues (VOQs). The feedback-based scheme is named round-robin with adaptable frame size (RR-AF) arbitration. The frame size in RR-AF is adaptably changed by the serviced and unserviced traffic. If a switch is stable, the switch provides 100% throughput. Here, it is proved that RR-AF can achieve 100% throughput under uniform admissible traffic. Switches with crosspoint buffers need to consider the transmission delays, or round-trip times to define the crosspoint buffer size. As the buffered crossbar switch can be physically located far from the input ports, actual round-trip times can be non-negligible. To support non-negligible round-trip times in a buffered crossbar switch, the crosspoint buffer size needs to be increased. To satisfy this demand, this dissertation investigates how to select the crosspoint buffer size under non-negligible round trip times and under uniform traffic. With the analysis of stability margin, the relationship between the crosspoint buffer size and round-trip time is derived. Considering that CICB switches deliver higher performance than lB switches and require no speedup, this dissertation investigates the maximum throughput performance that these switches can achieve. It is shown that CICB switches without speedup achieve 100% throughput under any admissible traffic through a fluid model. In addition, a new hybrid scheme, based on longest queue-first (as input arbitration) and longest column occupancy first (as output arbitration) is proposed, which achieves 100% throughput under uniform and non-uniform traffic patterns. In order to give a better insight of the feedback nature of arbitration scheme for CICB switches, a frame-based round-robin arbitration scheme with explicit feedback control (FRE) is introduced. FRE dynamically sets the frame size according to the input load and to the accumulation of cells in a VOQ. FRE is used as the input arbitration scheme and it is combined with RR, PRR, and FRE as output arbitration schemes. These combined schemes deliver high performance under uniform and nonuniform traffic models using a buffered crossbar with one-cell crosspoint buffers. The novelty of FRE lies in that each VOQ sets the frame size by an adjustable parameter, Δ(i,j) which indicates the degree of service needed by VOQ(i, j). This value is adjusted according to the input loading and the accumulation of cells experienced in previous service cycles. This dissertation also explores an analysis technique based on feedback control theory. This methodology is proposed to study the stability of arbitration and matching schemes for packet switches. A continuous system is used and a control model is used to emulate a queuing system. The technique is applied to a matching scheme. In addition, the study shows that the dwell time, which is defined as the time a queue receives service in a service opportunity, is a factor that affects the stability of a queuing system. This feedback control model is an alternative approach to evaluate the stability of arbitration and matching schemes

Building Internet caching systems for streaming media delivery

The proxy has been widely and successfully used to cache the static Web objects fetched by a client so that the subsequent clients requesting the same Web objects can be served directly from the proxy instead of other sources faraway, thus reducing the server\u27s load, the network traffic and the client response time. However, with the dramatic increase of streaming media objects emerging on the Internet, the existing proxy cannot efficiently deliver them due to their large sizes and client real time requirements.;In this dissertation, we design, implement, and evaluate cost-effective and high performance proxy-based Internet caching systems for streaming media delivery. Addressing the conflicting performance objectives for streaming media delivery, we first propose an efficient segment-based streaming media proxy system model. This model has guided us to design a practical streaming proxy, called Hyper-Proxy, aiming at delivering the streaming media data to clients with minimum playback jitter and a small startup latency, while achieving high caching performance. Second, we have implemented Hyper-Proxy by leveraging the existing Internet infrastructure. Hyper-Proxy enables the streaming service on the common Web servers. The evaluation of Hyper-Proxy on the global Internet environment and the local network environment shows it can provide satisfying streaming performance to clients while maintaining a good cache performance. Finally, to further improve the streaming delivery efficiency, we propose a group of the Shared Running Buffers (SRB) based proxy caching techniques to effectively utilize proxy\u27s memory. SRB algorithms can significantly reduce the media server/proxy\u27s load and network traffic and relieve the bottlenecks of the disk bandwidth and the network bandwidth.;The contributions of this dissertation are threefold: (1) we have studied several critical performance trade-offs and provided insights into Internet media content caching and delivery. Our understanding further leads us to establish an effective streaming system optimization model; (2) we have designed and evaluated several efficient algorithms to support Internet streaming content delivery, including segment caching, segment prefetching, and memory locality exploitation for streaming; (3) having addressed several system challenges, we have successfully implemented a real streaming proxy system and deployed it in a large industrial enterprise

Signaling in 3-D integrated circuits, benefits and challenges

Three-dimensional (3-D) or vertical integration is a design and packaging paradigm that can mitigate many of the increasing challenges related to the design of modern integrated systems. 3-D circuits have recently been at the spotlight, since these circuits provide a potent approach to enhance the performance and integrate diverse functions within amulti-plane stack. Clock networks consume a great portion of the power dissipated in a circuit. Therefore, designing a low-power clock network in synchronous circuits is an important task. This requirement is stricter for 3-D circuits due to the increased power densities. Synchronization issues can be more challenging for 3-D circuits since a clock path can spread across several planes with different physical and electrical characteristics. Consequently, designing low power clock networks for 3-D circuits is an important issue. Resonant clock networks are considered efficient low-power alternatives to conventional clock distribution schemes. These networks utilize additional inductive circuits to reduce power while delivering a full swing clock signal to the sink nodes. In this research, a design method to apply resonant clocking to synthesized clock trees is proposed. Manufacturing processes for 3-D circuits include some additional steps as compared to standard CMOS processes which makes 3-D circuits more susceptible to manufacturing defects and lowers the overall yield of the bonded 3-D stack. Testing is another complicated task for 3-D ICs, where pre-bond test is a prerequisite. Pre-bond testability, in turn, presents new challenges to 3-D clock network design primarily due to the incomplete clock distribution networks prior to the bonding of the planes. A design methodology of resonant 3-D clock networks that support wireless pre-bond testing is introduced. To efficiently address this issue, inductive links are exploited to wirelessly transmit the clock signal to the disjoint resonant clock networks. The inductors comprising the LC tanks are used as the receiver circuit for the links, essentially eliminating the need for additional circuits and/or interconnect resources during pre-bond test. Recent FPGAs are quite complex circuits which provide reconfigurablity at the cost of lower performance and higher power consumption as compared to ASIC circuits. Exploiting a large number of programmable switches, routing structures are mainly responsible for performance degradation in FPAGs. Employing 3-D technology can providemore efficient switches which drastically improve the performance and reduce the power consumption of the FPGA. RRAM switches are one of the most promising candidates to improve the FPGA routing architecture thanks to their low on-resistance and non-volatility. Along with the configurable switches, buffers are the other important element of the FPGAs routing structure. Different characteristics of RRAM switches change the properties of signal paths in RRAM-based FPGAs. The on resistance of RRAMswitches is considerably lower than CMOS pass gate switches which results in lower RC delay for RRAM-based routing paths. This different nature in critical path and signal delay in turn affect the need for intermediate buffers. Thus the buffer allocation should be reconsidered. In the last part of this research, the effect of intermediate buffers on signal propagation delay is studied and a modified buffer allocation scheme for RRAM-based FPGA routing path is proposed

Interconnection Networks for High-Performance Stream Computing with FPGA Clusters

Tohoku University佐野健太郎課

Adaptive Database Systems Based On Query Feedback and Cached Results

This dissertation explores the query optimization technique of using cached results and feedback for improving performance of database systems. Cached results and experience obtained by running queries are used to save execution time for follow–up queries, adapt data and system parameters, and improve overall system performance. First, we develop a framework which integrates query optimization and cache management. The optimizer is capable of generating efficient query plans using previous query results cached on the disk. Alternative methods to access and update the caches are considered by the optimizer based on cost estimation. Different cache management strategies are also included in this framework for comparison. Empirical performance study verifies the advantage and practicality of this framework. To help the optimizer in selecting the best plan, we propose a novel approach for providing accurate but cost-effective selectivity estimation. Distribution of attribute values is regressed in real time, using actual query result sizes obtained as feedback, to make accurate selectivity estimation. This method avoids the expensive off-line database access overhead required by the conventional methods and adapts fairly well to updates and query locality. This is verified empirically. To execute a query plan more efficiently, a buffer pool is usually provided for caching data pages in memory to reduce disk accesses. We enhance buffer utilization by devising a buffer allocation scheme for recurring queries using page fault feedback obtained from previous executions. Performance improvement of this scheme is shown by empirical examples and a systematic simulation

Traffic and resource management in content-centric networks (design and evaluation)

Dans les dernières années, l utilisation d Internet a sensiblement changé en passant d un modèle de communication centré sur les machines á un centré sur les contenus. La plus part de services utilisés par les clients d Internet aujourd hui sont déjà centré sur les contenus même et pas sur leurs emplacement. Dans ce contexte, beaucoup de projets de recherche proposent un changement de l architecture de l Internet, en mettent des contenu identifié par leur nom au centre du réseau. Ce group de proposition est identifiés sous le nom de Information Centric Networking (ICN). Cette thèse se focalise sur la proposition Content-Centric Network (CCN). Dans une premier temps, nous analysons les performance du modèle de communication CCN en se concentrent sur le partage de la bande passante et de la mémoire et en proposant des formules pour la caractérisation du temps de transfert. Deuxièmement, nous proposons un protocole de contrôle de congestion et des mécanismes de forwarding pour CCN. En particulier on présent un premier mécanisme de contrôle de congestion, Interest Control Protocol (ICP), qui utilise une fenêtre contrôlé avec le mécanisme Additive Increase Multiplicative Decrease au récepteur. En complément avec ça, nous présentons un mécanisme distribué (hop-by-hop) pour obtenir une détection/réaction à la congestion plus rapide. Nous proposons aussi une modification d'ICP en implémentant le mécanisme Remote Adaptive Active Queue Management pour exploiter efficacement le multi-chemin. En fin, nous présentons un mécanisme de forwarding distribué qui base ses décisions sur des mesure de qualité d interface par chaque préfixe disponible dans les tableaux de routage.The advent of the World Wide Web has radically changed Internet usage from host-to-host to service access and data retrieval. The majority of services used by Internet s clients are content-centric (e.g. web). However, the original Internet revolves around host-to-host communication for which it was conceived. Even if Internet has been able to address the challenges offered by new applications, there is an evident mismatch between the architecture and its current usage. Many projects in national research agencies propose to redesign the Internet architecture around named data. Such research efforts are identified under the name of Information Centric Networking. This thesis focuses on the Content-Centric Networking (CCN) proposition. We first analyze the CCN communication model with particular focus on the bandwidth and storage sharing performance, We compute closed formulas for data delivery time, that we use in the second part of the thesis as guideline for network protocol design. Second, we propose some CCN congestion control and forwarding mechanisms. We present a first window based receiver driven flow control protocol, Interest Control Protocol (ICP). We also introduce a hop-by-hop congestion control mechanism to obtain early congestion detection and reaction. We then extend the original ICP congestion control protocol implementing a Remote Adaptive Active Queue Management mechanism in order to efficiently exploit heterogeneous (joint/disjoint) network paths. Finally, we introduce a distributed forwarding mechanism that bases its decisions on per prefix and per interface quality measurement without impacting the system scalability.PARIS-Télécom ParisTech (751132302) / SudocSudocFranceF