FPGA Frequency Domain Based Gps Coarse Acquisition Processor using FFT

The Global Positioning System or GPS is a satellite based technology that has gained widespread use worldwide in civilian and military applications. Direct Sequence Spread spectrum (DSSS) is the method whereby the data transmitted by the satellite and received by user is kept secure, low power and relatively noise-immune. The first step required in the GPS operation is to perform a lock on the incoming signal, both with respect to time synchronization and frequency resolution. Because of the need for reduced time to lock and also reduced hardware, algorithms based in the frequency domain have been developed. These algorithms take advantage of the time to frequency matrix operation known as the fast Fourier transform or FFT. For this thesis, a Direct Sequence Spread Spectrum Coarse Acquisition code processor based on the FFT was implemented in VHDL and targeted to a Xilinx Virtex –II Pro Field Programmable Gate Array (FPGA). The use of the FFT allows simultaneous lock on coarse acquisition (C/A) code and carrier frequency. Because of hardware limitations, a novel technique of sub-sampling is used in this system to obtain data block sizes that match hardware limitations. In addition, design challenges related to scheduling and timing were addressed, allowing a system with 19 pipeline stages to be built. The system, which fits on a Xilinx Virtex-II pro XC2VP70 FPGA, uses 10 ms of data to perform the lock with 5.5 ms of processing time at 100 MHz and theoretically can operate on signals 20 db below the noise floor

Designing parameterizable hardware IPs in a model-based design environment for high-level synthesis

Model-based hardware design allows one to map a single model to multiple hardware and/or software architectures, essentially eliminating one of the major limitations of manual coding in C or RTL. Model-based design for hardware implementation has traditionally offered a limited set of microarchitectures, which are typically suitable only for some application scenarios. In this article we illustrate how digital signal processing (DSP) algorithms can be modeled as flexible intellectual property blocks to be used within the popular Simulink model-based design environment. These blocks are written in C and are designed for both functional simulation and hardware implementation, including architectural design space exploration and hardware implementation through high-level synthesis. A key advantage of our modeling approach is that the very same bit-accurate model is used for simulation and high-level synthesis. To prove the feasibility of our proposed approach, we modeled a fast Fourier transform (FFT) algorithm and synthesized it for different DSP applications with very different performance and cost requirements. We also implemented a high-level-synthesis (HLS) intellectual property (IP) generator that can generate flexible FFT HLS-IP blocks that can be mapped to multiple micro-/macroarchitectures, to enable design space exploration as well as being used for functional simulation in the Simulink environment.</jats:p

Adaptive Interference Mitigation in GPS Receivers

Satellite navigation systems (GNSS) are among the most complex radio-navigation systems, providing positioning, navigation, and timing (PNT) information. A growing number of public sector and commercial applications rely on the GNSS PNT service to support business growth, technical development, and the day-to-day operation of technology and socioeconomic systems. As GNSS signals have inherent limitations, they are highly vulnerable to intentional and unintentional interference. GNSS signals have spectral power densities far below ambient thermal noise. Consequently, GNSS receivers must meet high standards of reliability and integrity to be used within a broad spectrum of applications. GNSS receivers must employ effective interference mitigation techniques to ensure robust, accurate, and reliable PNT service. This research aims to evaluate the effectiveness of the Adaptive Notch Filter (ANF), a precorrelation mitigation technique that can be used to excise Continuous Wave Interference (CWI), hop-frequency and chirp-type interferences from GPS L1 signals. To mitigate unwanted interference, state-of-the-art ANFs typically adjust a single parameter, the notch centre frequency, and zeros are constrained extremely close to unity. Because of this, the notch centre frequency converges slowly to the target frequency. During this slow converge period, interference leaks into the acquisition block, thus sabotaging the operation of the acquisition block. Furthermore, if the CWI continuously hops within the GPS L1 in-band region, the subsequent interference frequency is locked onto after a delay, which means constant interference occurs in the receiver throughout the delay period. This research contributes to the field of interference mitigation at GNSS's receiver end using adaptive signal processing, predominately for GPS. This research can be divided into three stages. I first designed, modelled and developed a Simulink-based GPS L1 signal simulator, providing a homogenous test signal for existing and proposed interference mitigation algorithms. Simulink-based GPS L1 signal simulator provided great flexibility to change various parameters to generate GPS L1 signal under different conditions, e.g. Doppler Shift, code phase delay and amount of propagation degradation. Furthermore, I modelled three acquisition schemes for GPS signals and tested GPS L1 signals acquisition via coherent and non-coherent integration methods. As a next step, I modelled different types of interference signals precisely and implemented and evaluated existing adaptive notch filters in MATLAB in terms of Carrier to Noise Density (\u1d436/\u1d4410), Signal to Noise Ratio (SNR), Peak Degradation Metric, and Mean Square Error (MSE) at the output of the acquisition module in order to create benchmarks. Finally, I designed, developed and implemented a novel algorithm that simultaneously adapts both coefficients in lattice-based ANF. Mathematically, I derived the full-gradient term for the notch's bandwidth parameter adaptation and developed a framework for simultaneously adapting both coefficients of a lattice-based adaptive notch filter. I evaluated the performance of existing and proposed interference mitigation techniques under different types of interference signals. Moreover, I critically analysed different internal signals within the ANF structure in order to develop a new threshold parameter that resets the notch bandwidth at the start of each subsequent interference frequency. As a result, I further reduce the complexity of the structural implementation of lattice-based ANF, allowing for efficient hardware realisation and lower computational costs. It is concluded from extensive simulation results that the proposed fully adaptive lattice-based provides better interference mitigation performance and superior convergence properties to target frequency compared to traditional ANF algorithms. It is demonstrated that by employing the proposed algorithm, a receiver is able to operate with a higher dynamic range of JNR than is possible with existing methods. This research also presents the design and MATLAB implementation of a parameterisable Complex Adaptive Notch Filer (CANF). Present analysis on higher order CANF for detecting and mitigating various types of interference for complex baseband GPS L1 signals. In the end, further research was conducted to suppress interference in the GPS L1 signal by exploiting autocorrelation properties and discarding some portion of the main lobe of the GPS L1 signal. It is shown that by removing 30% spectrum of the main lobe, either from left, right, or centre, the GPS L1 signal is still acquirable

Transceivers with positioning capabilities

The objective of this work is the analysis of various algorithms for the acquisition of GNSS signals and find an efficient acquisition algorithm that can be implemented on a software-based receiver