Accurate Interconnection Length Estimations for Predictions Early in the Design Cycle

Important layout properties of electronic circuits include space requirements and interconnection lengths. In the process of designing these circuits, a reliable pre-layout interconnection length estimation is essential for improving placement and routing techniques. Donath found an upper bound for the average interconnection length that follows the trends of experimentally observed average lengths. Yet, this upper bound deviates from the experimental value by a factor ffi 2, which is not sufficiently accurate for some applications. We show that we obtain a significantly more accurate estimate by taking into account the inherent features of the optimal placement process. Keywords: Interconnection length estimates, Donath's hierarchical placement, Rent's rule, Occupancy probability. 1 INTRODUCTION The production of VLSI and ULSI computer chips requires the layout (placement and routing) of the (logical) chip design onto a physical carrier. With the advent of high level description la..