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κ³ μ DRAM μΈν°νμ΄μ€λ₯Ό μν μ μ λ° μ¨λμ λκ°ν ν΄λ‘ ν¨μ€μ μμ μ€λ₯ κ΅μ κΈ° μ€κ³
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Όλ¬Έ (λ°μ¬) -- μμΈλνκ΅ λνμ : 곡과λν μ κΈ°Β·μ 보곡νλΆ, 2021. 2. μ λκ· .To cope with problems caused by the high-speed operation of the dynamic random access memory (DRAM) interface, several approaches are proposed that are focused on the clock path of the DRAM. Two delay-locked loop (DLL) based schemes, a forwarded-clock (FC) receiver (RX) with self-tracking loop and a quadrature error corrector, are proposed. Moreover, an open-loop based scheme is presented for drift compensation in the clock distribution. The open-loop scheme consumes less power consumption and reduces design complexity.
The FC RX uses DLLs to compensate for voltage and temperature (VT) drift in unmatched memory interfaces. The self-tracking loop consists of two-stage cascaded DLLs to operate in a DRAM environment. With the write training and the proposed DLL, the timing relationship between the data and the sampling clock is always optimal. The proposed scheme compensates for delay drift without relying on data transitions or re-training. The proposed FC RX is fabricated in 65-nm CMOS process and has an active area containing 4 data lanes of 0.0329 mm2. After the write training is completed at the supply voltage of 1 V, the measured timing margin remains larger than 0.31-unit interval (UI) when the supply voltage drifts in the range of 0.94 V and 1.06 V from the training voltage, 1 V. At the data rate of 6.4 Gb/s, the proposed FC RX achieves an energy efficiency of 0.45 pJ/bit.
Contrary to the aforementioned scheme, an open-loop-based voltage drift compensation method is proposed to minimize power consumption and occupied area. The overall clock distribution is composed of a current mode logic (CML) path and a CMOS path. In the proposed scheme, the architecture of the CML-to-CMOS converter (C2C) and the inverter is changed to compensate for supply voltage drift. The bias generator provides bias voltages to the C2C and inverters according to supply voltage for delay adjustment. The proposed clock tree is fabricated in 40 nm CMOS process and the active area is 0.004 mm2. When the supply voltage is modulated by a sinusoidal wave with 1 MHz, 100 mV peak-to-peak swing from the center of 1.1 V, applying the proposed scheme reduces the measured root-mean-square (RMS) jitter from 3.77 psRMS to 1.61 psRMS. At 6 GHz output clock, the power consumption of the proposed scheme is 11.02 mW.
A DLL-based quadrature error corrector (QEC) with a wide correction range is proposed for the DRAM whose clocks are distributed over several millimeters. The quadrature error is corrected by adjusting delay lines using information from the phase error detector. The proposed error correction method minimizes increased jitter due to phase error correction by setting at least one of the delay lines in the quadrature clock path to the minimum delay. In addition, the asynchronous calibration on-off scheme reduces power consumption after calibration is complete. The proposed QEC is fabricated in 40 nm CMOS process and has an active area of 0.048 mm2. The proposed QEC exhibits a wide correctable error range of 101.6 ps and the remaining phase errors are less than 2.18Β° from 0.8 GHz to 2.3 GHz clock. At 2.3 GHz, the QEC contributes 0.53 psRMS jitter. Also, at 2.3 GHz, the power consumption is reduced from 8.89 mW to 3.39 mW when the calibration is off.λ³Έ λ
Όλ¬Έμμλ λμ λλ€ μ‘μΈμ€ λ©λͺ¨λ¦¬ (DRAM)μ μλκ° μ¦κ°ν¨μ λ°λΌ ν΄λ‘ ν¨μ€μμ λ°μν μ μλ λ¬Έμ μ λμ²νκΈ° μν μΈ κ°μ§ νλ‘λ€μ μ μνμλ€. μ μν νλ‘λ€ μ€ λ λ°©μλ€μ μ§μ°λ기루ν (delay-locked loop) λ°©μμ μ¬μ©νμκ³ λλ¨Έμ§ ν λ°©μμ λ©΄μ κ³Ό μ λ ₯ μλͺ¨λ₯Ό μ€μ΄κΈ° μν΄ μ€ν 루ν λ°©μμ μ¬μ©νμλ€. DRAMμ λΉμ ν© μμ κΈ° ꡬ쑰μμ λ°μ΄ν° ν¨μ€μ ν΄λ‘ ν¨μ€ κ°μ μ§μ° λΆμΌμΉλ‘ μΈν΄ μ μ λ° μ¨λ λ³νμ λ°λΌ μ
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νμ λ° νλ νμμ΄ μ€μ΄λλ λ¬Έμ λ₯Ό ν΄κ²°νκΈ° μν΄ μ§μ°λ기루νλ₯Ό μ¬μ©νμλ€. μ μν μ§μ°λ기루ν νλ‘λ DRAM νκ²½μμ λμνλλ‘ λ κ°μ μ§μ°λ기루νλ‘ λλμλ€. λν μ΄κΈ° μ°κΈ° νλ ¨μ ν΅ν΄ λ°μ΄ν°μ ν΄λ‘μ νμ΄λ° λ§μ§ κ΄μ μμ μ΅μ μ μμΉμ λ μ μλ€. λ°λΌμ μ μνλ λ°©μμ λ°μ΄ν° μ²μ΄ μ λ³΄κ° νμνμ§ μλ€. 65-nm CMOS 곡μ μ μ΄μ©νμ¬ λ§λ€μ΄μ§ μΉ©μ 6.4 Gb/sμμ 0.45 pJ/bitμ μλμ§ ν¨μ¨μ κ°μ§λ€. λν 1 Vμμ μ°κΈ° νλ ¨ λ° μ§μ°λ기루νλ₯Ό κ³ μ μν€κ³ 0.94 Vμμ 1.06 VκΉμ§ κ³΅κΈ μ μμ΄ λ°λμμ λ νμ΄λ° λ§μ§μ 0.31 UIλ³΄λ€ ν° κ°μ μ μ§νμλ€.
λ€μμΌλ‘ μ μνλ νλ‘λ ν΄λ‘ λΆν¬ νΈλ¦¬μμ μ μ λ³νλ‘ μΈν΄ ν΄λ‘ ν¨μ€μ μ§μ°μ΄ λ¬λΌμ§λ κ²μ μμ μ μν λ°©μκ³Ό λ¬λ¦¬ μ€ν 루ν λ°©μμΌλ‘ 보μνμλ€. κΈ°μ‘΄ ν΄λ‘ ν¨μ€μ μΈλ²ν°μ CML-to-CMOS λ³νκΈ°μ ꡬ쑰λ₯Ό λ³κ²½νμ¬ λ°μ΄μ΄μ€ μμ± νλ‘μμ μμ±ν κ³΅κΈ μ μμ λ°λΌ λ°λλ λ°μ΄μ΄μ€ μ μμ κ°μ§κ³ μ§μ°μ μ‘°μ ν μ μκ² νμλ€. 40-nm CMOS 곡μ μ μ΄μ©νμ¬ λ§λ€μ΄μ§ μΉ©μ 6 GHz ν΄λ‘μμμ μ λ ₯ μλͺ¨λ 11.02 mWλ‘ μΈ‘μ λμλ€. 1.1 V μ€μ¬μΌλ‘ 1 MHz, 100 mV νΌν¬ ν¬ νΌν¬λ₯Ό κ°μ§λ μ¬μΈν μ±λΆμΌλ‘ κ³΅κΈ μ μμ λ³μ‘°νμμ λ μ μν λ°©μμμμ μ§ν°λ κΈ°μ‘΄ λ°©μμ 3.77 psRMSμμ 1.61 psRMSλ‘ μ€μ΄λ€μλ€.
DRAMμ μ‘μ κΈ° ꡬ쑰μμ λ€μ€ μμ ν΄λ‘ κ°μ μμ μ€μ°¨λ μ‘μ λ λ°μ΄ν°μ λ°μ΄ν° μ ν¨ μ°½μ κ°μμν¨λ€. μ΄λ₯Ό ν΄κ²°νκΈ° μν΄ μ§μ°λ기루νλ₯Ό λμ
νκ² λλ©΄ μ¦κ°λ μ§μ°μΌλ‘ μΈν΄ μμμ΄ κ΅μ λ ν΄λ‘μμ μ§ν°κ° μ¦κ°νλ€. λ³Έ λ
Όλ¬Έμμλ μ¦κ°λ μ§ν°λ₯Ό μ΅μννκΈ° μν΄ μμ κ΅μ μΌλ‘ μΈν΄ μ¦κ°λ μ§μ°μ μ΅μννλ μμ κ΅μ νλ‘λ₯Ό μ μνμλ€. λν μ ν΄ μνμμ μ λ ₯ μλͺ¨λ₯Ό μ€μ΄κΈ° μν΄ μμ μ€μ°¨λ₯Ό κ΅μ νλ νλ‘λ₯Ό μ
λ ₯ ν΄λ‘κ³Ό λΉλκΈ°μμΌλ‘ λ μ μλ λ°©λ² λν μ μνμλ€. 40-nm CMOS 곡μ μ μ΄μ©νμ¬ λ§λ€μ΄μ§ μΉ©μ μμ κ΅μ λ²μλ 101.6 psμ΄κ³ 0.8 GHz λΆν° 2.3 GHzκΉμ§μ λμ μ£Όνμ λ²μμμ μμ κ΅μ κΈ°μ μΆλ ₯ ν΄λ‘μ μμ μ€μ°¨λ 2.18Β°λ³΄λ€ μλ€. μ μνλ μμ κ΅μ νλ‘λ‘ μΈν΄ μΆκ°λ μ§ν°λ 2.3 GHzμμ 0.53 psRMSμ΄κ³ κ΅μ νλ‘λ₯Ό κ»μ λ μ λ ₯ μλͺ¨λ κ΅μ νλ‘κ° μΌμ‘μ λμΈ 8.89 mWμμ 3.39 mWλ‘ μ€μ΄λ€μλ€.Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Thesis Organization 4
Chapter 2 Background on DRAM Interface 5
2.1 Overview 5
2.2 Memory Interface 7
Chapter 3 Background on DLL 11
3.1 Overview 11
3.2 Building Blocks 15
3.2.1 Delay Line 15
3.2.2 Phase Detector 17
3.2.3 Charge Pump 19
3.2.4 Loop filter 20
Chapter 4 Forwarded-Clock Receiver with DLL-based Self-tracking Loop for Unmatched Memory Interfaces 21
4.1 Overview 21
4.2 Proposed Separated DLL 25
4.2.1 Operation of the Proposed Separated DLL 27
4.2.2 Operation of the Digital Loop Filter in DLL 31
4.3 Circuit Implementation 33
4.4 Measurement Results 37
4.4.1 Measurement Setup and Sequence 38
4.4.2 VT Drift Measurement and Simulation 40
Chapter 5 Open-loop-based Voltage Drift Compensation in Clock Distribution 46
5.1 Overview 46
5.2 Prior Works 50
5.3 Voltage Drift Compensation Method 52
5.4 Circuit Implementation 57
5.5 Measurement Results 61
Chapter 6 Quadrature Error Corrector with Minimum Total Delay Tracking 68
6.1 Overview 68
6.2 Prior Works 70
6.3 Quadrature Error Correction Method 73
6.4 Circuit Implementation 82
6.5 Measurement Results 88
Chapter 7 Conclusion 96
Bibliography 98
μ΄λ‘ 102Docto