A new look at the conditions for the synthesis of speed-independent circuits

This paper presents a set of sufficient conditions for the gate-level synthesis of speed-independent circuits when constrained to a given class of gate library. Existing synthesis methodologies are restricted to architectures that use simple AND-gates, and do not exploit the advantages offered by the existence of complex gates. The use of complex gates increases the speed and reduces the area of the circuits. These improvements are achieved because of (1) the elimination of the distributivity, signal persistency and unique minimal state requirements imposed by other techniques; (2) the reduction in the number of internal signals necessary to guarantee the synthesis; and finally (3) the utilization of optimization techniques to reduce the fan-in of the involved gates and the number of required memory elements.Peer ReviewedPostprint (published version

Hierarchical gate-level verification of speed-independent circuits

This paper presents a method for the verification of speed-independent circuits. The main contribution is the reduction of the circuit to a set of complex gates that makes the verification time complexity depend only on the number of state signals (C elements, RS flip-flops) of the circuit. Despite the reduction to complex gates, verification is kept exact. The specification of the environment only requires to describe the transitions of the input/output signals of the circuit and is allowed to express choice and non-determinism. Experimental results obtained from circuits with more than 500 gates show that the computational cost can be drastically reduced when using hierarchical verification.Peer ReviewedPostprint (published version

Relative timing based verification of timed circuits and systems

Journal ArticleAggressive timed circuits, including synchronous and asynchronous self-resetting circuits, are particularly challenging to design and verify due to complicated timing constraints that must hold to ensure correct operation. Identifying a small, sufficient, and easily verifiable set of relative timing constraints simplifies both design and verification. However, the manual identification of these constraints is a complex and error-prone process. This paper presents the first systematic algorithm to generate and optimize relative timing constraints sufficient to guarantee correctness. The algorithm has been implemented in our RTCG tool and has been applied to several real-life circuits. In all cases, the tool successfully generates a sufficient set of easily verifiable relative timing constraints. Moreover, the generated constraint sets are the same size or smaller than that of the hand-optimized constraints

A Unified Signal Transition Graph Model for Asynchronous Control Circuit Synthesis

Characterization of the behavior of an asynchronous system depending on the delay of components and wires is a major task facing designers. Some of these delays are outside the designer's control, and in practice may have to be assumed unbounded. The existing literature offers a number of analysis and specification models, but lacks a unified framework to verify directly if the circuit specification admits a correct implementation under these hypotheses. Our aim is to fill exactly this gap, offering both low-level (analysis-oriented) and high-level (specification-oriented) models for asynchronous circuits and the environment where they operate, together with strong equivalence results between the properties at the two levels. One interesting side result is the precise characterization of classical static and dynamic hazards in terms of our model. Consequently the designer can check the specification and directly decide if the behavior of any implementation will depend, e.g., on the delays of the signals described by such specification.\ud We also outline a design methodology based on our models, pointing out how they can be used to select appropriate high\ud and low-level models depending on the desired characteristics of the system

Visualisation and analysis of complex behaviours using structured occurrence nets

PhD ThesisA complex evolving system consists of a large number of sub-systems which may proceed concurrently and interact with each other or with the external environment, while its behaviour is subject to modification by other systems. Structured occurrence nets (sons) are a Petri net based formalism for modelling the behaviour of complex evolving systems. The concept extends that of occurrence nets, a formalism that can be used to record causality and concurrency information concerning a single execution of a system. In sons, multiple occurrence nets are combined using various types of relationships in order to represent dependencies between communicating and evolving sub-systems. The work presented in this thesis aims to develop a tool and extend existing methodology for structured representations of the behaviours of complex evolving system. The theoretical development focuses on the extension of existing son concepts. It addresses the issue of efficient son model checking and simulation, representations of alternative behaviour and time information, structuring son-based unfolding, and algorithms for constructing the unfolding. The implementation aims to develop tools for son-based model visualisation, simulation and analysis. An open source tool called SONCraft has been developed to support these functionalities. SONCraft provides a user-friendly graphical interface that facilitates model entry, supports interactive visual simulation, and allows the use of a set of analytical tools for model checking.supported in part by EPSRC EP/K001698/1 UNderstanding COmplex system eVolution through structurEd behaviouRs (UNCOVER) project