7 research outputs found
Statistical static timing analysis considering the impact of power supply noise in VLSI circuits
As semiconductor technology is scaled and voltage level is reduced, the impact
of the variation in power supply has become very significant in predicting the realistic
worst-case delays in integrated circuits. The analysis of power supply noise is inevitable
because high correlations exist between supply voltage and delay. Supply noise analysis
has often used a vector-based timing analysis approach. Finding a set of test vectors in
vector-based approaches, however, is very expensive, particularly during the design
phase, and becomes intractable for larger circuits in DSM technology.
In this work, two novel vectorless approaches are described such that increases
in circuit delay, because of power supply noise, can be efficiently, quickly estimated.
Experimental results on ISCAS89 circuits reveal the accuracy and efficiency of my
approaches: in s38417 benchmark circuits, errors on circuit delay distributions are less
than 2%, and both of my approaches are 67 times faster than the traditional vector-based
approach. Also, the results show the importance of considering care-bits, which sensitize
the longest paths during the power supply noise analysis
A static pattern-independent technique for power grid voltage integrity verification
Design verification must include the power grid. Checking that the voltage on the power grid does not drop by more than some critical threshold is a very difficult problem, for at least two reasons: i) the obviously large size of the power grids for modern high-performance chips, and ii) the difficulty of setting up the right simulation conditions for the power grid that provide some measure of a realistic worst case voltage drop. The huge number of possible circuit operational modes or workloads makes it impossible to do exhaustive analysis. We propose a static technique for power grid verification, where static is in the sense of static timing analysis, meaning that it does not depend on, nor require, user-specified stimulus to drive a simulation. The verification is posed as an optimization problem under user-supplied current constraints. We propose that current constraints are the right kind of abstraction to use in order to develop a practical methodology for power grid verification. We present our verification approach, and report on the results of applying it to a number of test-case power grids