A self-reconfigurable hardware architecture for mesh arrays using single/double vertical track switches

科研費報告書収録論文(課題番号:14380138・基盤研究(B)(2)・14～16/研究代表者:堀口, 進 死亡(奥様 堀口悦子)/超高速ノンブロック・ネットワーク構成方式に関する研究

A Fault Diagnosis Scheme and Its Quality Issue in Reconfigurable Array Architecture

In this paper, we propose an efficient diagnosis scheme to detect and locate the switching network defects/faults in reconfigurable array architecture. This diagnosis scheme performs the test of switching network based on the scan path and fault intersection test methodology to locate the faults occurring in the switching network. After the diagnosis of switching network, the processing element (PE) test can then be initiated through the good switches and links. Errors in testing that cause a good switch, link or PE to be considered as a bad one is called "killing error". The issue of killing error in testing is addressed and the probability of killing error for our diagnosis technique is analyzed and shown to be extremely low. The significance of this approach is the ability to detect and locate the multiple faults in switches, links, and PEs with low testing circuit overhead, and to offer the good test quality in linear diagnosis time.Facultad de Informátic