AN APPROACH FOR LOW LEAKAGE POWER BY POWER GATING STACK TECHNIQUE

Clock gating (CG) and power gating (PG) the two most widely used techniques to reduce dynamic power and leakage power respectively, are expected to be integrated together effectively. Normally, the implementation of CG leads to some redundant operations, which provides the opportunity to apply PG. In this brief, we have proposed an activity-driven fine-grained CG and PG integration. For the implementation of XOR-based CG we have intro-duce an optimized bus-specific-clock-gating (OBSC) scheme to improve traditional gating.It chooses only a subset of flip-flops (FFs) to be gated selectively, and the problem of gated FF selection is reduced from exponential complexity into linear. Then those combinational logics, which completely depend on the outputs of gated FFs, are performing redundant operations. They can be power gated, and the clock enable signal generated by OBSC is used as the sleep signal. A minimum average idle time concept is proposed to determine whether the insertion of PG will lead to energy reduction.The simulation results show that 25.07% dynamic power can be reduced by OBSC, and 50.19% active leakage power can be saved by PG

A scalable algorithm for RTL insertion of gated clocks based on ODCs computation

In this paper, we propose a new algorithm for automatic clock-gating insertion applicable at the register transfer level (RTL). The basic rationale of our approach is to eliminate redundant computations performed by temporally unobservable blocks through aggressive exploitation of observability don't care (ODC) conditions. ODCs are efficiently detected from an RTL description by focusing only on data-path modules with easily detectable input unobservability conditions. ODCs are then propagated in the form of logic expressions toward the registers by backward traversal and levelization of the design. Finally, the logic expressions are mapped onto hardware to provide control signals to the clock-gating logic at a reduced cost in area and speed. The technique is characterized by fast processing time, high scalability to large designs, and tight user control on clock-gating overhead. Our approach is compatible with standard industrial design flows, and reduces power consumption significantly with a small overhead in delay and area. Experimental results obtained on a set of industrial RTL designs containing several tens of thousands of gates show average power reductions of around 42%. On the same examples, the application of traditional clock-gating leads to average savings reductions close to 29%