3 research outputs found
A reconfigurable, power-scalable Rake receiver IP for W-CDMA
During the last few years, the wireless market has experienced an exponential growth. 2G systems are essentially voice-oriented: the main innovation expected from 3G ones is the ubiquitous Internet and multimedia fruition. The transition from 2G to 3G provides both opportunities and challenges: one way to make this migration as smooth as possible relies on the employment of reconfigurable architectures. In this paper, a reconfigurable Rake receiver for W-CDMA is proposed. Very promising results from the physical implementation on a XCV300E have been obtained
Low Power Adaptive Equaliser Architectures for Wireless LMMSE Receivers
Power consumption requires critical consideration during system design for portable wireless
communication devices as it has a direct influence on the battery weight and volume required
for operation. Wideband Code Division Multiple Access (W-CDMA) techniques are favoured
for use in future generation mobile communication systems. This thesis investigates novel low
power techniques for use in system blocks within a W-CDMA adaptive linear minimum mean
squared error (LMMSE) receiver architecture. Two low power techniques are presented for
reducing power dissipation in the LMS adaptive filter, this being the main power consuming
block within this receiver. These low power techniques are namely the decorrelating transform,
this is a differential coefficient technique, and the variable length update algorithm which is a
dynamic tap-length optimisation technique.
The decorrelating transform is based on the principle of reducing the wordlength of filter
coefficients by using the computed difference between adjacent coefficients in calculation of
the filter output. The effect of reducing the wordlength of filter coefficients being presented to
multipliers in the filter is a reduction in switching activity within the multiplier thus reducing
power consumed. In the case of the LMS adaptive filter, with coefficients being continuously
updated, the decorrelating transform is applied to these calculated coefficients with minimal
hardware or computational overhead. The correlation between filter coefficients is exploited to
achieve a wordlength reduction from 16 bits down to 10 bits in the FIR filter block.
The variable length update algorithm is based on the principle of optimising the number of
operational filter taps in the LMS adaptive filter according to operating conditions. The number
of taps in operation can be increased or decreased dynamically according to the mean squared
error at the output of the filter. This algorithm is used to exploit the fact that when the SNR in
the channel is low the minimum mean squared error of the short equaliser is almost the same
as that of the longer equaliser. Therefore, minimising the length of the equaliser will not result
in poorer MSE performance and there is no disadvantage in having fewer taps in operation. If
fewer taps are in operation then switching will not only be reduced in the arithmetic blocks but
also in the memory blocks required by the LMS algorithm and FIR filter process. This reduces
the power consumed by both these computation intensive functional blocks. Power results are
obtained for equaliser lengths from 73 to 16 taps and for operation with varying input SNR.
This thesis then proposes that the variable length LMS adaptive filter is applied in the adaptive
LMMSE receiver to create a low power implementation. Power consumption in the receiver
is reduced by the dynamic optimisation of the LMS receiver coefficient calculation. A
considerable power saving is seen to be achieved when moving from a fixed length LMS
implementation to the variable length design. All design architectures are coded in Verilog
hardware description language at register transfer level (RTL). Once functional specification
of the design is verified, synthesis is carried out using either Synopsys DesignCompiler or
Cadence BuildGates to create a gate level netlist. Power consumption results are determined at
the gate level and estimated using the Synopsys DesignPower tool