4 research outputs found
A Radiation Tolerant Phase Locked Loop Design for Digital Electronics
With decreasing feature sizes, lowered supply voltages and increasing operating frequencies,
the radiation tolerance of digital circuits is becoming an increasingly important
problem. Many radiation hardening techniques have been presented in the literature for
combinational as well as sequential logic. However, the radiation tolerance of clock generation
circuitry has received scant attention to date. Recently, it has been shown that in
the deep submicron regime, the clock network contributes significantly to the chip level
Soft Error Rate (SER). The on-chip Phase Locked Loop (PLL) is particularly vulnerable to
radiation strikes. In this thesis, we present a radiation hardened PLL design. Each of the
components of this design-the voltage controlled oscillator (VCO), the phase frequency
detector (PFD) and the charge pump/loop filter-are designed in a radiation tolerant manner.
Whenever possible, the circuit elements used in our PLL exploit the fact that if a gate
is implemented using only PMOS (NMOS) transistors then a radiation particle strike can
result only in a logic 0 to 1 (1 to 0) flip. By separating the PMOS and NMOS devices,
and splitting the gate output into two signals, extreme high levels of radiation tolerance
are obtained. Our design uses two VCOs (with cross-coupled inverters) and charge pumps,
so that a strike on any one is compensated by the other. Our PLL is tested for radiation
immunity for critical charge values up to 250fC. Our SPICE-based results demonstrate that
after exhaustively striking all circuit nodes, the worst case jitter of our hardened PLL is just
37.4 percent. In the worst case, our PLL returns to the locked state in 2 cycles of the VCO clock,
after a radiation strike. These numbers are significant improvements over those of the best
previously reported approaches
Detecting Tangled Logic Structures in VLSI Netlists
This thesis proposes a new problem of identifying large and tangled logic structures in a
synthesized netlist. Large groups of cells that are highly interconnected to each other can
often create potential routing hotspots that require special placement constraints. They can
also indicate problematic clumps of logic that either require resynthesis to reduce wiring
demand or specialized datapath placement. At a glance, this formulation appears similar
to conventional circuit clustering, but there are two important distinctions. First, we are
interested in finding large groups of cells that represent entire logic structures like adders
and decoders, as opposed to clusters with only a handful of cells. Second, we seek to pull
out only the structures of interest, instead of assigning every cell to a cluster to reduce
problem complexity. This work proposes new metrics for detecting structures based on
Rent’s rule that, unlike traditional cluster metrics, are able to fairly differentiate between
large and small groups of cells. Next, we demonstrate how these metrics can be applied to
identify structures in a netlist. Finally, our experiments demonstrate the ability to predict
and alleviate routing hotspots on a real industry design using our metrics and method
Phase Noise Analyses and Measurements in the Hybrid Memristor-CMOS Phase-Locked Loop Design and Devices Beyond Bulk CMOS
Phase-locked loop (PLLs) has been widely used in analog or mixed-signal integrated circuits. Since there is an increasing market for low noise and high speed devices, PLLs are being employed in communications. In this dissertation, we investigated phase noise, tuning range, jitter, and power performances in different architectures of PLL designs. More energy efficient devices such as memristor, graphene, transition metal di-chalcogenide (TMDC) materials and their respective transistors are introduced in the design phase-locked loop.
Subsequently, we modeled phase noise of a CMOS phase-locked loop from the superposition of noises from its building blocks which comprises of a voltage-controlled oscillator, loop filter, frequency divider, phase-frequency detector, and the auxiliary input reference clock. Similarly, a linear time-invariant model that has additive noise sources in frequency domain is used to analyze the phase noise. The modeled phase noise results are further compared with the corresponding phase-locked loop designs in different n-well CMOS processes.
With the scaling of CMOS technology and the increase of the electrical field, the problem of short channel effects (SCE) has become dominant, which causes decay in subthreshold slope (SS) and positive and negative shifts in the threshold voltages of nMOS and pMOS transistors, respectively. Various devices are proposed to continue extending Moore\u27s law and the roadmap in semiconductor industry. We employed tunnel field effect transistor owing to its better performance in terms of SS, leakage current, power consumption etc. Applying an appropriate bias voltage to the gate-source region of TFET causes the valence band to align with the conduction band and injecting the charge carriers. Similarly, under reverse bias, the two bands are misaligned and there is no injection of carriers. We implemented graphene TFET and MoS2 in PLL design and the results show improvements in phase noise, jitter, tuning range, and frequency of operation. In addition, the power consumption is greatly reduced due to the low supply voltage of tunnel field effect transistor