A Low Jitter Wideband Fractional-N Subsampling Phase Locked Loop (SSPLL)

Frequency synthesizers have become a crucial building block in the evolution of modern communication systems and consumer electronics. The spectral purity performance of frequency synthesizers limits the achievable data-rate and presents a noise-power tradeoff. For communication standards such as LTE where the channel spacing is a few kHz, the synthesizers must provide high frequencies with sufficiently wide frequency tuning range and fine frequency resolutions. Such stringent performance must be met with a limited power and small chip area. In this thesis a wideband fractional-N frequency synthesizer based on a subsampling phase locked loop (SSPLL) is presented. The proposed synthesizer which has a frequency resolution less than 100Hz employs a digital fractional controller (DFC) and a 10-bit digital-to-time converter (DTC) to delay the rising edges of the reference clock to achieve fractional phase lock. For fast convergence of the delay calibration, a novel two-step delay correlation loop (DCL) is employed. Furthermore, to provide optimum settling and jitter performance, the loop transfer characteristics during frequency acquisition and phase-lock are decoupled using a dual input loop filter (DILF). The fractional-N sub-sampling PLL (FNSSPLL) is implemented in a TSMC 40nm CMOS technology and occupies a total active area of 0.41mm^2. The PLL operates over frequency range of 2.8 GHz to 4.3 GHz (42% tuning range) while consuming 9.18mW from a 1.1V supply. The integrated jitter performance is better than 390 fs across all fractional frequency channel. The worst case fractional spur of -48.3 dBc occurs at a 650 kHz offset for a 3.75GHz fractional channel. The in-band phase noise measured at a 200 kHz offset is -112.5 dBc/Hz

New strategies for low noise, agile PLL frequency synthesis

Phase-Locked Loop based frequency synthesis is an essential technique employed in wireless communication systems for local oscillator generation. The ultimate goal in any design of frequency synthesisers is to generate precise and stable output frequencies with fast switching and minimal spurious and phase noise. The conflict between high resolution and fast switching leads to two separate integer synthesisers to satisfy critical system requirements. This thesis concerns a new sigma-delta fractional-N synthesiser design which is able to be directly modulated at high data rates while simultaneously achieving good noise performance. Measured results from a prototype indicate that fast switching, low noise and spurious free spectra are achieved for most covered frequencies. The phase noise of the unmodulated synthesiser was measured −113 dBc/Hz at 100 kHz offset from the carrier. The intermodulation effect in synthesisers is capable of producing a family of spurious components of identical form to fractional spurs caused in quantisation process. This effect directly introduces high spurs on some channels of the synthesiser output. Numerical and analytic results describing this effect are presented and amplitude and distribution of the resulting fractional spurs are predicted and validated against simulated and measured results. Finally an experimental arrangement, based on a phase compensation technique, is presented demonstrating significant suppression of intermodulation-borne spurs. A new technique, pre-distortion noise shaping, is proposed to dramatically reduce the impact of fractional spurs in fractional-N synthesisers. The key innovation is the introduction in the bitstream generation process of carefully-chosen set of components at identical offset frequencies and amplitudes and in anti-phase with the principal fractional spurs. These signals are used to modify the Σ-Δ noise shaping, so that fractional spurs are effectively cancelled. This approach can be highly effective in improving spectral purity and reduction of spurious components caused by the Σ-Δ modulator, quantisation noise, intermodulation effects and any other circuit factors. The spur cancellation is achieved in the digital part of the synthesiser without introducing additional circuitry. This technique has been convincingly demonstrated by simulated and experimental results

Test bench solutions for advanced GNSS receivers : implementation, automation, and application

Considerable study has been devoted to the implementation of GNSS receivers for diverse applications, and to finding solutions to some of the non-idealities associated with such receivers. However, not much research is devoted to innovations in their performance evaluation, even though this is an integral step in the overall implementation process. This research work attempts to address this issue through three different perspectives: by focusing on innovation in the testing procedures and test-bench implementation, its automation and its application to advanced multi-frequency, multi-constellation GPS and Galileo receivers. Majority of this research was conducted within the GREAT, GRAMMAR, and FUGAT projects funded by EU FP6/FP7 and TEKES respectively, during which the author was responsible for designing test-scenarios and performing validations of the implemented receiver solution. The first part of the research is devoted to the study and design of sources of test signals for an advanced GNSS receiver test-bench. An in-depth background literature study was conducted on software-based GNSS signal simulators to trace their evolution over the past two decades. Keeping their special features and limitations in view, recommendations have been made on the optimum architecture and essential features within such simulators for testing of advanced receivers. This resulted in the implementation of an experimental software-based simulator capable of producing GPS L1 and Galileo E1 signals at intermediate frequency. Another solution investigated was a GNSS Sampled Data Generator (SDG) based on wideband sampling. This included designing the entire radio front-end operating on the bandpass-sampling principle. The low noise amplifier designed as part of this SDG has been implemented on a printed circuit board. Phase noise (PN) from the radio front-end’s local frequency generator (LFG) is a source of error that has hitherto not been included in any GNSS signal simulator. Furthermore, the characterization of the baseband tracking loops in presence of this phase noise has not yet been included in the typical receiver test scenarios. The second part of this research attempts to create mathematical models representing the LFG’s phase noise contribution, first for a free running oscillator and later for a complete phase-locked loop (PLL). The effect of such phase noise was studied on the baseband correlation performance of GPS and Galileo receivers. The results helped to demonstrate a direct relation between the PN and the baseband tracking performance, thus helping to define guidelines for radio front-end PLL circuit design in order to maintain a minimum baseband tracking performance within the GNSS receiver. The final part of this research work focusses on describing the automated test-bench developed at Tampere University of Technology (TUT) for analyzing the overall performance of multi-frequency multi-constellation GNSS receivers. The proposed testbench includes a data capture tool to extract internal process information, and the overall controlling software, called automated performance evaluation tool, that is able to communicate between all modules for hands-free, one-button-click testing of GNSS receivers. Furthermore, these tools have been applied for the single frequency GPS L1 performance testing of the TUTGNSS receiver, with recommendations on how they can be adapted to testing of advanced multi-frequency, multi-constellation receivers