Design of High Speed Split SAR ADC With Improved Linearity

Abstract: Recently low power Analog to Digital Converters(ADCs) have been developed for many energy constrained applications such as wireless sensor networks and bio-medical applications. Successive approximation register (SAR) ADC are good candidates for low power applications and widely used for low energy application due to its minimum analog blocks. The static linearity performance in terms of the integral nonlinearity and differential nonlinearity and the parasitic effects of the split DAC, are analyzed. A code-randomized calibration technique is done to correct the conversion nonlinearity in the conventional SAR ADC, which is verified by behavioral simulation. Here the SAR ADC is designed in such a way that the control module completely control the splitting up of modules and the speed of operation is changed using low level input bits.A dedicated multiplexer can be used to minimize the capacitor array structure.The control module controls the clock signal and determines the time at which the analog signal should enter the SAR logic.On attaining control over the time of arrival of input signals the speed of conversion can be increased and power utilisation can be minimised

High speed – energy efficient successive approximation analog to digital converter using tri-level switching

This thesis reports issues and design methods used to achieve high-speed and high-resolution Successive Approximation Register analog to digital converters (SAR ADCs). A major drawback of this technique relates to the mismatch in the binary ratios of capacitors which causes nonlinearity. Another issue is the use of large capacitors due to nonlinear effect of parasitic capacitance. Nonlinear effect of capacitor mismatch is investigated in this thesis. Based on the analysis, a new Tri-level switching algorithm is proposed to reduce the matching requirement for capacitors in SAR ADCs. The integral non-linearity (INL) and the differential non-linearity (DNL) of the proposed scheme are reduced by factor of two over conventional SAR ADC, which is the lowest compared to the previously reported schemes. In addition, the switching energy of the proposed scheme is reduced by 98.02% compared with the conventional SAR architecture. A new correction method to solve metastability error of comparator based on a novel design approach is proposed which reduces the required settling time about 1.1τ for each conversion cycle. Based on the above proposed methods two SAR ADCs: an 8-bit SAR ADC with 50MS/sec sampling rate, and a 10-bit SAR split ADC with 70 MS/sec sampling rate have been designed in 0.18μm Silterra complementary metal oxide semiconductor (CMOS) technology process which works at 1.2V supply voltage and input voltage of 2.4Vp-p. The 8-bit ADC digitizes 25MHz input signal with 48.16dB signal to noise and distortion ratio (SNDR) and 52.41dB spurious free dynamic range (SFDR) while consuming about 589μW. The figure of merit (FOM) of this ADC is 56.65 fJ/conv-step. The post layout of the 10-bit ADC with 1MHz input frequency produces SNDR, SFDR and effective number of bits (ENOB) of 57.1dB, 64.05dB and 9.17Bit, respectively, while its DNL and INL are -0.9/+2.8 least significant bit (LSB) and -2.5/+2.7 LSB, respectively. The total power consumption, including digital, analog and reference power, is 1.6mW. The FOM is 71.75fJ/conv. step

Digital Background Self-Calibration Technique for Compensating Transition Offsets in Reference-less Flash ADCs

This Dissertation focusses on proving that background calibration using adaptive algorithms are low-cost, stable and effective methods for obtaining high accuracy in flash A/D converters. An integrated reference-less 3-bit flash ADC circuit has been successfully designed and taped out in UMC 180 nm CMOS technology in order to prove the efficiency of our proposed background calibration. References for ADC transitions have been virtually implemented built-in in the comparators dynamic-latch topology by a controlled mismatch added to each comparator input front-end. An external very simple DAC block (calibration bank) allows control the quantity of mismatch added in each comparator front-end and, therefore, compensate the offset of its effective transition with respect to the nominal value. In order to assist to the estimation of the offset of the prototype comparators, an auxiliary A/D converter with higher resolution and lower conversion speed than the flash ADC is used: a 6-bit capacitive-DAC SAR type. Special care in synchronization of analogue sampling instant in both ADCs has been taken into account. In this thesis, a criterion to identify the optimum parameters of the flash ADC design with adaptive background calibration has been set. With this criterion, the best choice for dynamic latch architecture, calibration bank resolution and flash ADC resolution are selected. The performance of the calibration algorithm have been tested, providing great programmability to the digital processor that implements the algorithm, allowing to choose the algorithm limits, accuracy and quantization errors in the arithmetic. Further, systematic controlled offset can be forced in the comparators of the flash ADC in order to have a more exhaustive test of calibration

Integrated Circuit Design for Miniaturized, Trackable, Ultrasound Based Biomedical Implants

This thesis focuses on the design of an ultrasonography compatible implantable sensor platform, as a novel approach that implements a miniaturized, battery-less, real-time trackable parallel biosensing system. In addition to the frontend circuit, a sub-nW fully integrated pH sensor is designed in a way that can be easily integrated with the proposed sonography-compatible sensor platform. Combining the two integrated circuits together, the whole system will be able to map in vivo physiological information acquired from a distributed set of sensors on top of the ultrasound movie, leading to the idea envisioned as “augmented ultrasonography”. Implemented in a 0.18 μm technology, an ultrasound power and data frontend circuit is designed to enable medical sensing implants to operate in an ultrasonography compatible way. When placed within the field of view of an imaging transducer, the frontend circuit harvests the power through a piece of piezo crystal from a minimally modified brightness-mode (B-mode) ultrasound imaging process that is commonly adopted in modern medical practices. The implant can also establish bi-directional data communication channels with the imaging transducer, allowing data to be transmitted in a way synchronized to the frame rate of the B-mode film. The design of the circuit is made possible by a combination of ultra-low-power circuit techniques and novel frontend circuit topologies, as imaging ultrasound waves in the form of short pulses with extremely low duty cycle poses challenges that has not previously seen in other implantable sensor systems. The proposed prototype achieves a total area of 0.6mm² for the integrated circuit (IC), as well as 71mm theoretical maximum implantable depth (up to 40 mm is verified experimentally). These two together give opportunities for this design to become the next generation solution for deep-tissue bio-sensing implants. Realized using the same 0.18 μm technology, the fully integrated pH sensor is designed to deliver accurate pH readouts, at a reasonable speed of 1 sample per second, while consuming only 0.72 nW of power. Using an ion-sensitive field effect transistor (ISFET) and reference field effect transistor pair (REFET), the IC requires minimum additional post fabrication to deliver 10-bit resolution pH readouts at an end-to-end sensitivity of 65.8 LSB/pH. When working as a standalone device, this work advances the state-of-the-art of ISFET based pH sensor design. With an addition of 0.46 mm² of area, it is possible to integrate it with the ultrasound sonography compatible implant platform. This potential integration will further advance the vision of the augmented ultrasonography: real-time display of physiological information in a B-mode film, with the help from a distributed bio-sensor system for deep-tissue physiology monitoring