Design And Implementation Of A Hardware Level Content Networking Front End Device

The bandwidth and speed of network connections are continually increasing. The speed increase in network technology is set to soon outpace the speed increase in CMOS technology. This asymmetrical growth is beginning to causing software applications that once worked with then current levels of network traffic to flounder under the new high data rates. Processes that were once executed in software now have to be executed, partially if not wholly in hardware. One such application that could benefit from hardware implementation is high layer routing. By allowing a network device to peer into higher layers of the OSI model, the device can scan for viruses, provide higher quality-of-service (QoS), and efficiently route packets. This thesis proposes an architecture for a device that will utilize hardware-level string matching to distribute incoming requests for a server farm. The proposed architecture is implemented in VHDL, synthesized, and laid out on an Altera FPGA

A Power-Efficient Tcam Architecture For Network Forwarding Tables

Stringent memory access and search speed requirements are two of the main bottlenecks in wire speed processing. Most viable search engines are implemented in content addressable memories (CAMs). CAMs have high operational speed advantage over other memory search algorithms. However, this performance advantage comes with a price of higher silicon area, and higher power consumption. Ternary CAMs (TCAM) are widely used for route lookup operations in networking applications. IP address prefix length distribution in the core routers shows a similar characteristic such that the prefixes with 24 or longer bits attract more than 50% of the traffic. Based on this statistical observation, we propose a TCAM architecture that can be used on top of the previously reported power saving techniques and it offers additional 30% reduction in power consumption. Furthermore, we model the dynamic power consumption in TCAM circuits due match, mismatch and don\u27t care activities. © 2006 Elsevier B.V. All rights reserved

A power-efficient TCAM architecture for network forwarding tables

Stringent memory access and search speed requirements are two of the main bottlenecks in wire speed processing. Most viable search engines are implemented in content addressable memories (CAMs). CAMs have high operational speed advantage over other memory search algorithms. However, this performance advantage comes with a price of higher silicon area, and higher power consumption. Ternary CAMs (TCAM) are widely used for route lookup operations in networking applications. IP address prefix length distribution in the core routers shows a similar characteristic such that the prefixes with 24 or longer bits attract more than 50% of the traffic. Based on this statistical observation, we propose a TCAM architecture that can be used on top of the previously reported power saving techniques and it offers additional 30% reduction in power consumption. Furthermore, we model the dynamic power consumption in TCAM circuits due match, mismatch and don\u27t care activities. (C) 2006 Elsevier B.V. All rights reserved