Transfer of innovation - using research tools for engineering education

In this article, the authors show how, in the pursuit of research results, they can obtain excellent tools and data for engineering education. In particular, they describe one example of computer architecture in the Computer Engineering Degree Programme at the University of Cádiz in Spain. This research topic is of particular importance as it influences the execution of a range of the computer’s I/O operations, due to operations of peripherals and information devices, and determines processor performance. The simulator used in research and teaching in several engineering degree programmes at the University of Cádiz is also demonstrated in this article

Architectural Verification of Four-instruction Superscalar Processor for MIPS I Instruction Set

The study undertaken in this thesis tries to tackle this inefficiency by having extra register locations other than the architectural registers called pseudo-registers, and a pointer scheme is followed to reference both architectural and pseudo registers. This scheme renames each logical destination register of an incoming instruction, to a pseudo register referenced by pointers called pseudo-pointers. Two separate lists of these pointers are maintained, one for all types of instructions and the other for only unspeculated instructions. When a branch instruction preceding the speculated instruction is evaluated and it is established that the prediction was correct, the machine state is altered by updating the pointer lists instead of moving the data. As the pointes are only 6-bits, the inefficiency is considerably reduced. This processor scheme is implemented using the Verilog hardware description language (HDL). The following study provides architectural details of each component used in the processor, stressing issues involved in the implementation and methods used to overcome these issues. This study also discusses verification methodology, documenting steps involved in compiling a 'c' program and loading it onto the simulated instructions cache and data cache for simulation. Finally, simulation results are presented for a sample 'c' program verifying the design