Improving Student Comprehension Through Interactive Microarchitecture Simulation and Visualization

The curricula of most Computer Science departments include at least one course on computer organization and assembly language. The seminal concepts covered by such courses bridge the gap between hardware and software by introducing multiple layers of abstraction. Appalachian State University introduces this material in the course “Introduction to Computer Systems.” The course uses the hypothetical LC-3 processor, as presented in Patt and Patel’s textbook “Introduction to Computing Systems: From Bits & Gates to C & Beyond (2nd edition).” Prior to the completion of the work presented in this thesis, tools existed for the assembly of LC-3 programs and simulation of the assembled code; however, no simulator existed to demonstrate the function of the microarchitectural level. In this thesis, research on educational simulators is presented, with an emphasis on microarchitectural and graphical style simulators. Multiple simulators were reviewed to determine which elements are pedagogically e?ective. Based on these ?ndings, a graphical microarchitecture simulator named lc3uarch was implemented. The simulator targets the microarchitectural level of the LC-3 processor. Student surveys responses indicated that the use of lc3uarch can help students comprehend the logic components of the LC-3 microarchitecture and provided ideas for making the tool more e?ective

A pedagogically targeted logic design and simulation tool

JLS is a GUI-based digital logic simulation tool specifically designed for use in a wide range of digital logic and computer organization courses. It is comparable in features and functionality to commercial products, but includes many student and instructor-friendly aspects not found in those products such as state-machine and truth table editors, extensive error checking, and multiple simulation-result views. Students quickly become proficient in its use, enabling them to concentrate on circuit design and debugging issues. The circuit drawing interface is convenient enough to allow instructors to use it for classroom presentations, and circuits can be modified and tested so quickly that it promotes exploring alternatives not prepared for in advance. Its non-interractive (batch) execution capability, with parameter settings, configuration files and textual output simplifies the grading of large numbers of student projects. Copyright 2007 ACM

JLS: A pedagogically targeted logic design and simulation tool

JLS is a GUI-based digital logic simulation tool specifically designed for use in a wide range of digital logic and computer organization courses. It is comparable in features and functionality to commercial products, but includes many student and instructor-friendly aspects not found in those products such as state-machine and truth table editors, extensive error checking, and multiple simulation result views. Students quickly become proficient in its use, enabling them to concentrate on circuit design and debugging issues. The circuit drawing interface is convenient enough to allow instructors to use it for classroom presentations, and circuits can be modified and tested so quickly that it promotes exploring alternatives not prepared for in advance