Hardware acceleration architectures for MPEG-Based mobile video platforms: a brief overview

This paper presents a brief overview of past and current hardware acceleration (HwA) approaches that have been proposed for the most computationally intensive compression tools of the MPEG-4 standard. These approaches are classified based on their historical evolution and architectural approach. An analysis of both evolutionary and functional classifications is carried out in order to speculate on the possible trends of the HwA architectures to be employed in mobile video platforms

Energy-efficient acceleration of MPEG-4 compression tools

We propose novel hardware accelerator architectures for the most computationally demanding algorithms of the MPEG-4 video compression standard-motion estimation, binary motion estimation (for shape coding), and the forward/inverse discrete cosine transforms (incorporating shape adaptive modes). These accelerators have been designed using general low-energy design philosophies at the algorithmic/architectural abstraction levels. The themes of these philosophies are avoiding waste and trading area/performance for power and energy gains. Each core has been synthesised targeting TSMC 0.09 μm TCBN90LP technology, and the experimental results presented in this paper show that the proposed cores improve upon the prior art

Modeling superimposed preeclampsia using Ang II (Angiotensin II) infusion in pregnant stroke-prone spontaneously hypertensive rats

Hypertensive disorders of pregnancy are the second leading cause of maternal deaths worldwide. Superimposed preeclampsia is an increasingly common problem and often associated with impaired placental perfusion. Understanding the underlying mechanisms and developing treatment options are crucial. The pregnant stroke-prone spontaneously hypertensive rat has impaired uteroplacental blood flow and abnormal uterine artery remodeling. We used Ang II (angiotensin II) infusion in pregnant stroke-prone spontaneously hypertensive rats to mimic the increased cardiovascular stress associated with superimposed preeclampsia and examine the impact on the maternal cardiovascular system and fetal development. Continuous infusion of Ang II at 500 or 1000 ng/kg per minute was administered from gestational day 10.5 until term. Radiotelemetry and echocardiography were used to monitor hemodynamic and cardiovascular changes, and urine was collected prepregnancy and throughout gestation. Uterine artery myography assessed uteroplacental vascular function and structure. Fetal measurements were made at gestational day 18.5, and placentas were collected for histological and gene expression analyses. The 1000 ng/kg per minute Ang II treatment significantly increased blood pressure (P<0.01), reduced cardiac output (P<0.05), and reduced diameter and increased stiffness of the uterine arteries (P<0.01) during pregnancy. The albumin:creatinine ratio was increased in both Ang II treatment groups (P<0.05; P<0.0001). The 1000 ng/kg per minute–treated fetuses were significantly smaller than vehicle treatment (P<0.001). Placental expression of Ang II receptors was increased in the junctional zone in 1000 ng/kg per minute Ang II–treated groups (P<0.05), with this zone showing depletion of glycogen content and structural abnormalities. Ang II infusion in pregnant stroke-prone spontaneously hypertensive rats mirrors hemodynamic, cardiac, and urinary profiles observed in preeclamptic women, with evidence of impaired fetal growth

Energy efficient enabling technologies for semantic video processing on mobile devices

Semantic object-based processing will play an increasingly important role in future multimedia systems due to the ubiquity of digital multimedia capture/playback technologies and increasing storage capacity. Although the object based paradigm has many undeniable benefits, numerous technical challenges remain before the applications becomes pervasive, particularly on computational constrained mobile devices. A fundamental issue is the ill-posed problem of semantic object segmentation. Furthermore, on battery powered mobile computing devices, the additional algorithmic complexity of semantic object based processing compared to conventional video processing is highly undesirable both from a real-time operation and battery life perspective. This thesis attempts to tackle these issues by firstly constraining the solution space and focusing on the human face as a primary semantic concept of use to users of mobile devices. A novel face detection algorithm is proposed, which from the outset was designed to be amenable to be offloaded from the host microprocessor to dedicated hardware, thereby providing real-time performance and reducing power consumption. The algorithm uses an Artificial Neural Network (ANN), whose topology and weights are evolved via a genetic algorithm (GA). The computational burden of the ANN evaluation is offloaded to a dedicated hardware accelerator, which is capable of processing any evolved network topology. Efficient arithmetic circuitry, which leverages modified Booth recoding, column compressors and carry save adders, is adopted throughout the design. To tackle the increased computational costs associated with object tracking or object based shape encoding, a novel energy efficient binary motion estimation architecture is proposed. Energy is reduced in the proposed motion estimation architecture by minimising the redundant operations inherent in the binary data. Both architectures are shown to compare favourable with the relevant prior art

High throughput and scalable architecture for unified transform coding in embedded H.264/AVC video coding systems

An innovative high throughput and scalable multi-transform architecture for H.264/AVC is presented in this paper. This structure can be used as a hardware accelerator in modern embedded systems to efficiently compute the 4×4 forward/inverse integer DCT, as well as the 2-D 4×4 / 2×2 Hadamard transforms. Moreover, its highly flexible design and hardware efficiency allows it to be easily scaled in terms of performance and hardware cost to meet the specific requirements of any given video coding application. Experimental results obtained using a Xilinx Virtex-4 FPGA demonstrate the superior performance and hardware efficiency levels provided by the proposed structure, which presents a throughput per unit of area at least 1.8× higher than other similar recently published designs. Furthermore, such results also showed that this architecture can compute, in realtime, all the above mentioned H.264/AVC transforms for video sequences with resolutions up to UHDV.info:eu-repo/semantics/publishedVersio