Design of A Low Power Low Voltage CMOS Opamp

In this paper a CMOS operational amplifier is presented which operates at 2V power supply and 1microA input bias current at 0.8 micron technology using non conventional mode of operation of MOS transistors and whose input is depended on bias current. The unique behaviour of the MOS transistors in subthreshold region not only allows a designer to work at low input bias current but also at low voltage. While operating the device at weak inversion results low power dissipation but dynamic range is degraded. Optimum balance between power dissipation and dynamic range results when the MOS transistors are operated at moderate inversion. Power is again minimised by the application of input dependant bias current using feedback loops in the input transistors of the differential pair with two current substractors. In comparison with the reported low power low voltage opamps at 0.8 micron technology, this opamp has very low standby power consumption with a high driving capability and operates at low voltage. The opamp is fairly small (0.0084 mm 2) and slew rate is more than other low power low voltage opamps reported at 0.8 um technology [1,2]. Vittoz at al [3] reported that slew rate can be improved by adaptive biasing technique and power dissipation can be reduced by operating the device in weak inversion. Though lower power dissipation is achieved the area required by the circuit is very large and speed is too small. So, operating the device in moderate inversion is a good solution. Also operating the device in subthreshold region not only allows lower power dissipation but also a lower voltage operation is achieved.Comment: 8 Pages, VLSICS Journa

Design methodology for ultra low-power analog circuits using next generation BSIM6 MOSFET compact model

The recently proposed BSIM6 bulk MOSFET compact model is set to replace the hitherto widely used BSIM3 and BSIM4 models as the de-facto industrial standard. Unlike its predecessors which were threshold voltage based, the BSIM6 core is charge based and thus physically continuous at all levels of inversion from linear operation to saturation. Hence, it lends itself conveniently for the use of a design methodology suited for low-power analog circuit design based on the inversion coefficient (IC) that has been extensively used in conjugation with the EIN model and allows to make simple calculations of, for example, transconductance efficiency, gain bandwidth product, etc. This methodology helps to make a near-optimal selection of transistor dimensions and operating points even in moderate and weak inversion regions. This paper will discuss the IC based design methodology and its application to the next generation BSIM6 compact MOSFET model. (C) 2013 Elsevier Ltd. All rights reserved

Ultra Small Antenna and Low Power Receiver for Smart Dust Wireless Sensor Networks

Wireless Sensor Networks have the potential for profound impact on our daily lives. Smart Dust Wireless Sensor Networks (SDWSNs) are emerging members of the Wireless Sensor Network family with strict requirements on communication node sizes (1 cubic centimeter) and power consumption (< 2mW during short on-states). In addition, the large number of communication nodes needed in SDWSN require highly integrated solutions. This dissertation develops new design techniques for low-volume antennas and low-power receivers for SDWSN applications. In addition, it devises an antenna and low noise amplifier co-design methodology to increase the level of design integration, reduce receiver noise, and reduce the development cycle. This dissertation first establishes stringent principles for designing SDWSN electrically small antennas (ESAs). Based on these principles, a new ESA, the F-Inverted Compact Antenna (FICA), is designed at 916MHz. This FICA has a significant advantage in that it uses a small-size ground plane. The volume of this FICA (including the ground plane) is only 7% of other state-of-the-art ESAs, while its efficiency (48.53%) and gain (-1.38dBi) are comparable to antennas of much larger dimensions. A physics-based circuit model is developed for this FICA to assist system level design at the earliest stage, including optimization of the antenna performance. An antenna and low noise amplifier (LNA) co-design method is proposed and proven to be valid to design low power LNAs with the very low noise figure of only 1.5dB. To reduce receiver power consumption, this dissertation proposes a novel LNA active device and an input/ouput passive matching network optimization method. With this method, a power efficient high voltage gain cascode LNA was designed in a 0.13um CMOS process with only low quality factor inductors. This LNA has a 3.6dB noise figure, voltage gain of 24dB, input third intercept point (IIP3) of 3dBm, and power consumption of 1.5mW at 1.0V supply voltage. Its figure of merit, using the typical definition, is twice that of the best in the literature. A full low power receiver is developed with a sensitivity of -58dBm, chip area of 1.1mm2, and power consumption of 2.85mW