A Wireless, High-Voltage Compliant, and Energy-Efficient Visual Intracortical Microstimulator

RÉSUMÉ L’objectif général de ce projet de recherche est la conception, la mise en oeuvre et la validation d’une interface sans fil intracorticale implantable en technologie CMOS avancée pour aider les personnes ayant une déficience visuelle. Les défis majeurs de cette recherche sont de répondre à la conformité à haute tension nécessaire à travers l’interface d’électrode-tissu (IET), augmenter la flexibilité dans la microstimulation et la surveillance multicanale, minimiser le budget de puissance pour un dispositif biomédical implantable, réduire la taille de l’implant et améliorer le taux de transmission sans fil des données. Par conséquent, nous présentons dans cette thèse un système de microstimulation intracorticale multi-puce basée sur une nouvelle architecture pour la transmission des données sans fil et le transfert de l’énergie se servant de couplages inductifs et capacitifs. Une première puce, un générateur de stimuli (SG) éconergétique, et une autre qui est un amplificateur de haute impédance se connectant au réseau de microélectrodes de l’étage de sortie. Les 4 canaux de générateurs de stimuli produisent des impulsions rectangulaires, demi-sinus (DS), plateau-sinus (PS) et autres types d’impulsions de courant à haut rendement énergétique. Le SG comporte un contrôleur de faible puissance, des convertisseurs numérique-analogiques (DAC) opérant en mode courant, générateurs multi-forme d’ondes et miroirs de courants alimentés sous 1.2 et 3.3V se servant pour l’interface entre les deux technologies utilisées. Le courant de stimulation du SG varie entre 2.32 et 220μA pour chaque canal. La deuxième puce (pilote de microélectrodes (MED)), une interface entre le SG et de l’arrangement de microélectrodes (MEA), fournit quatre niveaux différents de courant avec la valeur maximale de 400μA par entrée et 100μA par canal de sortie simultanément pour 8 à 16 sites de stimulation à travers les microélectrodes, connectés soit en configuration bipolaire ou monopolaire. Cette étage de sortie est hautement configurable et capable de délivrer une tension élevée pour satisfaire les conditions de l’interface à travers l’impédance de IET par rapport aux systèmes précédemment rapportés. Les valeurs nominales de plus grandes tensions d’alimentation sont de ±10V. La sortie de tension mesurée est conformément 10V/phase (anodique ou cathodique) pour les tensions d’alimentation spécifiées. L’incrémentation de tensions d’alimentation à ±13V permet de produire un courant de stimulation de 220μA par canal de sortie permettant d’élever la tension de sortie jusqu’au 20V par phase. Cet étage de sortie regroupe un commutateur haute tension pour interfacer une matrice des miroirs de courant (3.3V /20V), un registre à décalage de 32-bits à entrée sérielle, sortie parallèle, et un circuit dédié pour bloquer des états interdits.----------ABSTRACT The general objective of this research project is the design, implementation and validation of an implantable wireless intracortical interface in advanced CMOS technology to aid the visually impaired people. The major challenges in this research are to meet the required highvoltage compliance across electrode-tissue interface (ETI), increase lexibility in multichannel microstimulation and monitoring, minimize power budget for an implantable biomedical device, reduce the implant size, and enhance the data rate in wireless transmission. Therefore, we present in this thesis a multi-chip intracortical microstimulation system based on a novel architecture for wireless data and power transmission comprising inductive and capacitive couplings. The first chip is an energy-efficient stimuli generator (SG) and the second one is a highimpedance microelectrode array driver output-stage. The 4-channel stimuli-generator produces rectangular, half-sine (HS), plateau-sine (PS), and other types of energy-efficient current pulse. The SG is featured with low-power controller, current mode source- and sinkdigital- to-analog converters (DACs), multi-waveform generators, and 1.2V/3.3V interface current mirrors. The stimulation current per channel of the SG ranges from 2.32 to 220μA per channel. The second chip (microelectrode driver (MED)), an interface between the SG and the microelectrode array (MEA), supplies four different current levels with the maximum value of 400μA per input and 100μA per output channel. These currents can be delivered simultaneously to 8 to 16 stimulation sites through microelectrodes, connected either in bipolar or monopolar configuration. This output stage is highly-configurable and able to deliver higher compliance voltage across ETI impedance compared to previously reported designs. The nominal values of largest supply voltages are ±10V. The measured output compliance voltage is 10V/phase (anodic or cathodic) for the specified supply voltages. Increment of supply voltages to ±13V allows 220μA stimulation current per output channel enhancing the output compliance voltage up to 20V per phase. This output-stage is featured with a high-voltage switch-matrix, 3.3V/20V current mirrors, an on-chip 32-bit serial-in parallel-out shift register, and the forbidden state logic building blocks. The SG and MED chips have been designed and fabricated in IBM 0.13μm CMOS and Teledyne DALSA 0.8μm 5V/20V CMOS/DMOS technologies with silicon areas occupied by them 1.75 x 1.75mm2 and 4 x 4mm2 respectively. The measured DC power budgets consumed by low-and mid-voltage microchips are 2.56 and 2.1mW consecutively

Toward an energy-efficient high-voltage compliant visual intracortical multichannel stimulator

ABSTRACT: We present, in this paper, a new multichip system aimed toward building an implantable visual intracortical stimulation device. The objective is to deliver energy-optimum pulse patterns to neural sites with needed compliance voltage across high electrode–tissue interface impedance of implantable microelectrodes. The first chip is an energy-efficient stimuli generator (SG), and the second one is a high-impedance microelectrode array driver (MED) output stage. The fourchannel SG produces rectangular, half-sine, plateau-sine, and other types of current pulse with stimulation current ranging from 2.32 to 220 μA per channel. The microelectrode array driver is able to deliver 20 V per anodic or cathodic phase across the microelectrode–tissue interface for ±13 V power supplies. The MED supplies different current levels with the maximum value of 400 μA per input and 100 μA per output channel simultaneously to 8–16 stimulation sites through microelectrodes, connected either in bipolar or monopolar configuration. Both chips receive power via inductive link and data through capacitive coupling. The SG and MED chips have been fabricated in 0.13-μm CMOS and 0.8-μm 5-/20-V CMOS/double-diffused metal-oxidesemiconductor technologies. The measured dc power budgets consumed by low- and mid-voltage chips are 2.56 and 2.1 mW consecutively. The system, modular in architecture, is interfaced with a newly developed platinum-coated pyramidal microelectrode array. In vitro test results with 0.9% phosphate buffer saline show the microelectrode impedance of 70 Ωk at 1 kHz

Charge Pumps for Implantable Microstimulators in Low and High-Voltage Technologies

RÉSUMÉ L'objectif principal de cette thèse est de concevoir et mettre en œuvre une pompe de charge qui peut produire suffisamment de tension afin de l’implémenter à un système de prothèse visuelle, conçue par le laboratoire PolyStim neurotechnologies. Il a été constaté que l'une des parties les plus consommatrices d'énergie de l'ensemble du système de prothèse visuelle est la pompe de charge. En raison de la nature variable du tissu nerveux et de l'interface d’électrode, la tension nécessaire par stimuler le tissu nerveux est très élevé et consomme extrêmement d’énergie. En outre, afin de fournir du courant biphasique aux électrodes il faut produire des tensions positives et négatives. La génération de tension négative est très difficile, surtout dans les technologies à faible tension compte tenu des limites de la technologie. Le premier objectif du projet est de générer la haute tension nécessaire qui va consommer une faible puissance statique. La technologie de haute tension a été utilisée dans le but d’atteindre cet objectif. Le deuxième objectif est de générer la tension requise dans la technologie de basse tension et ainsi surmonter les limites de la technologie. Dans les deux cas, une attention particulière a été portée afin que personne ne latch-up apparaît pour le cycle négatif. L'architecture de la conception proposée a été présentée dans cette thèse. La pompe de charge a été conçu et mis en oeuvre à la fois dans la technologie CMOS 0,8 μm offert par TELEDYNE DALSA et technologie 0,13 μm CMOS offert par IBM. En raison de la tension requise, 0,8 μm technologie a été utilisée pour atteindre la sortie et conçu pour minimiser la consommation de puissance statique. La même architecture a été mise en oeuvre en technologie 0,13 μm pour enquêter sur la tension de sortie obtenue avec une faible consommation électrique. Les deux puces ont été testées en laboratoire PolyStim. Les résultats testés ont montré une variation moyenne très faible de déviation inférieure à 5% par rapport au résultat de simulation. Pour la conception en 0,8 µm, nous avons été en mesure d'obtenir plus de 25 V avec une consommation électrique très faible d’énergie statique de 3,846 mW et une charge d'entraînement maximum de 2 mA avec un maximum d'efficacité de 84,2%. Pour le même processus en 0,13 µm, les resultats ont été plus que 20V, 0,913 mW, 500 µA, et 85,2% respectivement.----------ABSTRACT The main objective of the thesis is to design and implement a charge pump that can produce enough voltage required to be implemented to the visual prosthesis system, designed by the PolyStim Neurotechnologies laboratory. It has been found that one of the most power consuming parts of the whole visual prosthesis system is the charge pump. Due to the variable nature of the nerve tissue and electrode interface, the required voltage of stimulating the nerve tissue is very high and thus extremely power consuming. Also, in order to provide biphasic current to the electrodes, there is a requirement of generating both positive and negative voltages. Generating negative voltage is very hard especially in low voltage technologies considering the technology limitations. The first objective of the project is to generate required high voltage that will consume low static power. High voltage technology has been used to achieve the goal. The second objective is to generate the required voltage in low voltage technology overcoming the technology limitations. In both cases, special care has been taken so that no latch-up occurs for the negative cycle. Architecture of the proposed design has been presented in this thesis. The charge pump has been designed and implemented in both 0.8 µm CMOS technology offered by TELEDYNE DALSA and 0.13 µm CMOS technology offered by IBM. Because of the required voltage, 0.8 µm technology has been used to achieve the output and designed to minimize the static power consumption. The same architecture has been implemented in 0.13 µm technology to investigate the achievable output voltage with low power consumption. Both the chips have been tested in polyStim laboratory. The tested results have shown very low variation of less than 5% average deflection from the simulation output. For the design in 0.8 µm, we have been able to get more than 25 V output with very low static power consumption of 3.846 mW and maximum drive load of 2 mA with maximum efficiency of 84.2%. For the same design in 0.13 µm, the outputs were more than 20V, 0.913 mW, 500 µA, and 85.2% respectively

Génération de stimuli efficaces en énergie pour la microstimulation électrique intracorticale

RÉSUMÉ Ce mémoire a comme objectif principal la mise en oeuvre de circuits dédiés à l’amélioration de l’efficacité de la stimulation électrique de tissus situés au niveau du cortex visuel primaire. Le stimulateur proposé permet la génération de nouveaux stimuli flexibles de forme exponentielle et demi-sinusoïdale dans l’optique de réduire la consommation de puissance globale de l’implant. En plus d’être potentiellement plus efficaces que les stimulations rectangulaires standard pour exciter les tissus, ces formes d’impulsions permettraient également de réduire la concentration d’ions toxiques relâchés par les électrodes. Le second objectif de ce projet est de permettre la stimulation à pleine échelle, soit au moins 150 µA, à travers l’interface microélectrode-tissus qui est caractérisée par une impédance élevée. Un étage de sortie à haute-tension a donc également été réalisé afin de générer des tensions d’alimentation d’environ ±9 V et d’augmenter ainsi l’excursion de tension des stimuli tout en étant entièrement intégré. Une architecture comportant deux circuits intégrés indépendants est proposée dans ce mémoire. Le générateur de stimuli est implémenté dans la technologie CMOS 0,18-µ m 1,8V/3,3V de TSMC afin de limiter sa consommation de puissance. Pour ce qui est de l’étage de sortie, il est intégré à l’aide du procédé C08E CMOS/DMOS 0,8-µ m 5V/20V de DALSA Semiconductors, technologie supportant les niveaux de tension requis.Les deux puces ainsi fabriquées ont été testées. L’intensité des stimuli rectangulaires couvre une plage de 1,6 à 167,2 µ A des erreurs de non-linéarité différentielle et intégrale de 0,10 et 0,16 LSB respectivement. Les impulsions exponentielles ont une plage dynamique de 34,36 dB pour une erreur de ±0,5 dB par rapport à la fonction théorique. La consommation de puissance du générateur de stimuli atteint en moyenne 29,1 µW en mode rectangulaire et de 28,5 à 88,3 µ W en mode exponentiel. Les résultats obtenus pour la demi-sinusoïde proviennent de simulations. En moyenne, 80,2 % de la durée des impulsions demi-sinusoïdales a une erreur inférieure à ±1 % par rapport à la fonction idéale. Le générateur de stimuli complet consomme de 46,7 à 199,1 µW en mode demi-sinusoïdal. En ce qui a trait à l’étage de sortie, des tensions de 8,95 et -8,46 V sont générées avec succès, permettant à l’excursion de tension d’atteindre 13,6 V à travers une charge de 100 kΩ.----------ABSTRACT This master thesis’ main objective is the implementation of circuits dedicated to electrical stimulation efficiency enhancement for tissues in the primary visual cortex. The proposed stimulator allows novel stimuli waveform generation such as flexible exponential and half-sine pulses in order to reduce the implant’s global power consumption. In addition of being potentially more efficient to excite neural tissues than standard rectangular pulse-based stimulations, these waveforms should also reduce toxic ions concentration released by the electrodes. Moreover, this project’s second objective is to allow full-scale stimulation, i.e., at least 150 µA, through high-impedance microelectrode-tissue interfaces. A high-voltage output stage has also been realized to generate ±9 V voltage supplies to increase the voltage swing while being fully-integrated. An architecture composed of two independent integrated circuits has been proposed. The stimuli generator is implemented in TSMC CMOS 0.18-µ m 1.8V/3.3V technology to limit its power consumption. On the other hand, the output stage is integrated in C08E CMOS/DMOS 0.8- µm 5V/20V process from DALSA Semiconductors as this technology supports the required voltage levels.These two fabricated chips were tested. Rectangular stimuli intensity varies from 1.6 to 167.2 µA with differential and integral nonlinearities of 0.10 and 0.16 LSB, respectively. Exponential pulses show a dynamic range of 34.36 dB for an error of ±0.5 dB with the theoretical waveform. The stimuli generator’s power consumption reaches an average of 29.1 µW in rectangular mode and from 28.5 to 88.3 µW in exponential mode. Half-sine results are obtained from simulations. An average of 80.2 % of half-sine pulse duration has an error lower than ±1 % with the ideal sine function. The whole stimuli generator consumes from 46.7 to 199.1 µW in half-sine mode. For the output stage, voltages of 8.95 and -8.46 V are successfully generated, allowing the output voltage compliance to reach 13.6 V through a 100 kΩ load. However, this chip dissipates 51.37 mW when operating normally

A programmable closed-loop recording and stimulating wireless system for behaving small laboratory animals

A portable 16-channels microcontroller-based wireless system for a bi-directional interaction with the central nervous system is presented in this work. The device is designed to be used with freely behaving small laboratory animals and allows recording of spontaneous and evoked neural activity wirelessly transmitted and stored on a personal computer. Biphasic current stimuli with programmable duration, frequency and amplitude may be triggered in real-time on the basis of the recorded neural activity as well as by the animal behavior within a specifically designed experimental setup. An intuitive graphical user interface was developed to configure and to monitor the whole system. The system was successfully tested through bench tests and in vivo measurements on behaving rats chronically implanted with multi-channels microwire arrays

Wireless Simultaneous Stimulation-and-Recording Device (SRD) to Train Cortical Circuits in Rat Somatosensory Cortex

The primary goal of this project is to develop a wireless system for simultaneous recording-and-stimulation (SRD) to deliver low amplitude current pulses to the primary somatosensory cortex (SI) of rats to activate and enhance an interhemispheric cortical pathway. Despite the existence of an interhemispheric connection between similar forelimb representations of SI cortices, forelimb cortical neurons respond only to input from the contralateral (opposite side) forelimb and not to input from the ipsilateral (same side) forelimb. Given the existence of this interhemispheric pathway we have been able to strengthen/enhance the pathway through chronic intracortical microstimulation (ICMS) in previous acute experiments of anesthetized rats. In these acute experiments strengthening the interhemispheric pathway also brings about functional reorganization whereby cortical neurons in forelimb cortex respond to new input from the ipsilateral forelimb. Having the ability to modify cortical circuitry will have important applications in stroke patients and could serve to rescue and/or enhance responsiveness in surviving cells around the stroke region. Also, the ability to induce functional reorganization within the deafferented cortical map, which follows limb amputation, will also provide a vehicle for modulating maladaptive cortical reorganization often associated with phantom limb pain leading to reduced pain. In order to increase our understanding of the observed functional reorganization and enhanced pathway, we need to be able to test these observations in awake and behaving animals and eventually study how these changes persist over a prolonged period of time. To accomplish this a system was needed to allow simultaneous recording and stimulation in awake rats. However, no such commercial or research system exists that meets all requirements for such an experiment. In this project we describe the (1) system design, (2) system testing, (3) system evaluation, and (4) system implementation of a wireless simultaneous stimulation-and-recording device (SRD) to be used to modulate cortical circuits in an awake rodent animal model

Multielectrode microstimulation for temporal lobe epilepsy

Multielectrode arrays may have several advantages compared to the traditional single macroelectrode brain electrical stimulation technique including less tissue damage due to implantation and the ability to deliver several spatio-temporal patterns of stimulation. Prior work on cell cultures has shown that multielectrode arrays are capable of completely stopping seizure-like spontaneous bursting events through a distributed asynchronous multi-site approach. In my studies, I used a similar approach for controlling seizures in a rat model of temporal lobe epilepsy. First, I developed a new method of electroplating in vivo microelectrode arrays for durably improving their impedance. I showed that microelectrode arrays electroplated through the new technique called sonicoplating, required the least amount of voltage in current controlled stimulation studies and also produced the least amplitude and duration of stimulation artifact compared to unplated, DC electroplated or pulse-plated microelectrodes. Second, using c-fos immunohistochemistry, I showed that 16-electrode sonicoplated microelectrode arrays can activate 5.9 times more neurons in the dorsal hippocampus compared to a single macroelectrodes while causing < 77% the tissue damage. Next, through open-loop multisite asynchronous microstimulation, I reduced seizure frequency by ~50% in the rodent model of temporal lobe epilepsy. Preliminary studies aimed at using the same stimulation protocol in closed-loop responsive and predictive seizure control did not stop seizures. Finally, through an internship at Medtronic Neuromodulation, I worked on developing and implementing a rapid algorithm prototyping research tool for closed-loop human deep brain stimulation applications.Ph.D

Bidirectional Neural Interface Circuits with On-Chip Stimulation Artifact Reduction Schemes

Bidirectional neural interfaces are tools designed to “communicate” with the brain via recording and modulation of neuronal activity. The bidirectional interface systems have been adopted for many applications. Neuroscientists employ them to map neuronal circuits through precise stimulation and recording. Medical doctors deploy them as adaptable medical devices which control therapeutic stimulation parameters based on monitoring real-time neural activity. Brain-machine-interface (BMI) researchers use neural interfaces to bypass the nervous system and directly control neuroprosthetics or brain-computer-interface (BCI) spellers. In bidirectional interfaces, the implantable transducers as well as the corresponding electronic circuits and systems face several challenges. A high channel count, low power consumption, and reduced system size are desirable for potential chronic deployment and wider applicability. Moreover, a neural interface designed for robust closed-loop operation requires the mitigation of stimulation artifacts which corrupt the recorded signals. This dissertation introduces several techniques targeting low power consumption, small size, and reduction of stimulation artifacts. These techniques are implemented for extracellular electrophysiological recording and two stimulation modalities: direct current stimulation for closed-loop control of seizure detection/quench and optical stimulation for optogenetic studies. While the two modalities differ in their mechanisms, hardware implementation, and applications, they share many crucial system-level challenges. The first method aims at solving the critical issue of stimulation artifacts saturating the preamplifier in the recording front-end. To prevent saturation, a novel mixed-signal stimulation artifact cancellation circuit is devised to subtract the artifact before amplification and maintain the standard input range of a power-hungry preamplifier. Additional novel techniques have been also implemented to lower the noise and power consumption. A common average referencing (CAR) front-end circuit eliminates the cross-channel common mode noise by averaging and subtracting it in analog domain. A range-adapting SAR ADC saves additional power by eliminating unnecessary conversion cycles when the input signal is small. Measurements of an integrated circuit (IC) prototype demonstrate the attenuation of stimulation artifacts by up to 42 dB and cross-channel noise suppression by up to 39.8 dB. The power consumption per channel is maintained at 330 nW, while the area per channel is only 0.17 mm2. The second system implements a compact headstage for closed-loop optogenetic stimulation and electrophysiological recording. This design targets a miniaturized form factor, high channel count, and high-precision stimulation control suitable for rodent in-vivo optogenetic studies. Monolithically integrated optoelectrodes (which include 12 µLEDs for optical stimulation and 12 electrical recording sites) are combined with an off-the-shelf recording IC and a custom-designed high-precision LED driver. 32 recording and 12 stimulation channels can be individually accessed and controlled on a small headstage with dimensions of 2.16 x 2.38 x 0.35 cm and mass of 1.9 g. A third system prototype improves the optogenetic headstage prototype by furthering system integration and improving power efficiency facilitating wireless operation. The custom application-specific integrated circuit (ASIC) combines recording and stimulation channels with a power management unit, allowing the system to be powered by an ultra-light Li-ion battery. Additionally, the µLED drivers include a high-resolution arbitrary waveform generation mode for shaping of µLED current pulses to preemptively reduce artifacts. A prototype IC occupies 7.66 mm2, consumes 3.04 mW under typical operating conditions, and the optical pulse shaping scheme can attenuate stimulation artifacts by up to 3x with a Gaussian-rise pulse rise time under 1 ms.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/147674/1/mendrela_1.pd

Neuromorphic-Based Neuroprostheses for Brain Rewiring: State-of-the-Art and Perspectives in Neuroengineering.

Neuroprostheses are neuroengineering devices that have an interface with the nervous system and supplement or substitute functionality in people with disabilities. In the collective imagination, neuroprostheses are mostly used to restore sensory or motor capabilities, but in recent years, new devices directly acting at the brain level have been proposed. In order to design the next-generation of neuroprosthetic devices for brain repair, we foresee the increasing exploitation of closed-loop systems enabled with neuromorphic elements due to their intrinsic energy efficiency, their capability to perform real-time data processing, and of mimicking neurobiological computation for an improved synergy between the technological and biological counterparts. In this manuscript, after providing definitions of key concepts, we reviewed the first exploitation of a real-time hardware neuromorphic prosthesis to restore the bidirectional communication between two neuronal populations in vitro. Starting from that 'case-study', we provide perspectives on the technological improvements for real-time interfacing and processing of neural signals and their potential usage for novel in vitro and in vivo experimental designs. The development of innovative neuroprosthetics for translational purposes is also presented and discussed. In our understanding, the pursuit of neuromorphic-based closed-loop neuroprostheses may spur the development of novel powerful technologies, such as 'brain-prostheses', capable of rewiring and/or substituting the injured nervous system

700mV low power low noise implantable neural recording system design

This dissertation presents the work for design and implementation of a low power, low noise neural recording system consisting of Bandpass Amplifier and Pipelined Analog to Digital Converter (ADC) for recording neural signal activities. A low power, low noise two stage neural amplifier for use in an intelligent Radio-Frequency Identification (RFID) based on folded cascode Operational Transconductance Amplifier (OTA) is utilized to amplify the neural signals. The optimization of the number of amplifier stages is discussed to achieve the minimum power and area consumption. The amplifier power supply is 0.7V. The midband gain of amplifier is 58.4dB with a 3dB bandwidth from 0.71 to 8.26 kHz. Measured input-referred noise and total power consumption are 20.7 μVrms and 1.90 μW respectively. The measured result shows that the optimizing the number of stages can achieve lower power consumption and demonstrates the neural amplifier's suitability for instu neutral activity recording. The advantage of power consumption of Pipelined ADC over Successive Approximation Register (SAR) ADC and Delta-Sigma ADC is discussed. An 8 bit fully differential (FD) Pipeline ADC for use in a smart RFID is presented in this dissertation. The Multiplying Digital to Analog Converter (MDAC) utilizes a novel offset cancellation technique robust to device leakage to reduce the input drift voltage. Simulation results of static and dynamic performance show this low power Pipeline ADC is suitable for multi-channel neural recording applications. The performance of all proposed building blocks is verified through test chips fabricated in IBM 180nm CMOS process. Both bench-top and real animal test results demonstrate the system's capability of recording neural signals for neural spike detection